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https://github.com/openhwgroup/cvw
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92 lines
2.3 KiB
C
92 lines
2.3 KiB
C
///////////////////////////////////////////////////////////////////////
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// spi.c
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//
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// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
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//
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// Purpose: SPI Controller API for bootloader
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//
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//
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the
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// “License”); you may not use this file except in compliance with the
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// License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work
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// distributed under the License is distributed on an “AS IS” BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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// implied. See the License for the specific language governing
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// permissions and limitations under the License.
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///////////////////////////////////////////////////////////////////////
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#include "spi.h"
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uint8_t spi_txrx(uint8_t byte) {
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spi_sendbyte(byte);
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waittx();
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return spi_readbyte();
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}
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uint8_t spi_dummy() {
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return spi_txrx(0xff);
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}
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uint64_t spi_read64() {
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uint64_t r;
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uint8_t rbyte;
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int i;
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for (i = 0; i < 8; i++) {
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spi_sendbyte(0xFF);
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}
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waittx();
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for (i = 0; i < 8; i++) {
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rbyte = spi_readbyte();
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r = r | (rbyte << ((8 - 1 - i)*8));
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}
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return r;
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}
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void spi_set_clock(uint32_t clkin, uint32_t clkout) {
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uint32_t div = (clkin/(2*clkout)) - 1;
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write_reg(SPI_SCKDIV, div);
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}
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// Initialize Sifive FU540 based SPI Controller
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void spi_init(uint32_t clkin) {
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// Enable interrupts
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write_reg(SPI_IE, 0x3);
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// Set TXMARK to 1. If the number of entries is < 1
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// IP's txwm field will go high.
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// Set RXMARK to 0. If the number of entries is > 0
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// IP's rwxm field will go high.
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write_reg(SPI_TXMARK, 1);
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write_reg(SPI_RXMARK, 0);
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// Set Delay 0 to default
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write_reg(SPI_DELAY0,
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SIFIVE_SPI_DELAY0_CSSCK(1) |
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SIFIVE_SPI_DELAY0_SCKCS(1));
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// Set Delay 1 to default
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write_reg(SPI_DELAY1,
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SIFIVE_SPI_DELAY1_INTERCS(1) |
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SIFIVE_SPI_DELAY1_INTERXFR(0));
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// Initialize the SPI controller clock to
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// div = (20MHz/(2*400kHz)) - 1 = 24 = 0x18
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write_reg(SPI_SCKDIV, 0x18);
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}
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