cvw/pipelined/testbench
2022-05-25 17:03:15 -07:00
..
common
fp
sdc
testbench-coremark_bare.sv
testbench-f64.sv
testbench-fp.sv single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
testbench-fpga.sv
testbench-linux.sv changes suggested by ben, hopefully fixing buildroot (which is now not running) 2022-05-20 18:42:38 -07:00
testbench.sv added logic to prevent cache line length from exceeding the max size of a burst. 2022-05-25 17:03:15 -07:00
testbench.sv.bak filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
tests-fp.vh single and double conversions pass all tests 2022-05-25 23:02:02 +00:00
tests.vh quit 2022-05-17 01:03:09 +00:00