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https://github.com/openhwgroup/cvw
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45 lines
1.6 KiB
Systemverilog
45 lines
1.6 KiB
Systemverilog
///////////////////////////////////////////
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// sync_r2w.sv
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//
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// Written: Clifford E Cummings 16 June 2005
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// Modified: james.stine@okstate.edu 19 February 2024
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//
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// Purpose: FIFO read-domain to write-domain synchronizer
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module sync_r2w #(parameter ADDRSIZE = 4)
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(wq2_rptr, rptr, wclk, wrst_n);
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input logic [ADDRSIZE:0] rptr;
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input logic wclk;
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input logic wrst_n;
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output logic [ADDRSIZE:0] wq2_rptr;
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logic [ADDRSIZE:0] wq1_rptr;
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always @(posedge wclk or negedge wrst_n)
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if (!wrst_n) {wq2_rptr,wq1_rptr} <= 0;
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else {wq2_rptr,wq1_rptr} <= {wq1_rptr,rptr};
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endmodule // sync_r2w
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