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https://github.com/openhwgroup/cvw
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66 lines
2.4 KiB
Systemverilog
66 lines
2.4 KiB
Systemverilog
///////////////////////////////////////////
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// rptr_empty.sv
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//
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// Written: Clifford E Cummings 16 June 2005
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// Modified: james.stine@okstate.edu 19 February 2024
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//
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// Purpose: FIFO read pointer and empty generation logic
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module rptr_empty #(parameter ADDRSIZE = 4)
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(rempty, raddr, rptr, rq2_wptr, rinc, rclk, rrst_n);
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input logic [ADDRSIZE:0] rq2_wptr;
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input logic rinc;
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input logic rclk;
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input logic rrst_n;
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output logic rempty;
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output logic [ADDRSIZE-1:0] raddr;
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output logic [ADDRSIZE :0] rptr;
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logic [ADDRSIZE:0] rbin;
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logic [ADDRSIZE:0] rgraynext;
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logic [ADDRSIZE:0] rbinnext;
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//-------------------
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// GRAYSTYLE2 pointer
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//-------------------
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always @(posedge rclk or negedge rrst_n)
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if (!rrst_n) {rbin, rptr} <= 0;
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else {rbin, rptr} <= {rbinnext, rgraynext};
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// Memory read-address pointer (okay to use binary to address memory)
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assign raddr = rbin[ADDRSIZE-1:0];
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assign rbinnext = rbin + (rinc & ~rempty);
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assign rgraynext = (rbinnext>>1) ^ rbinnext;
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//---------------------------------------------------------------
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// FIFO empty when the next rptr == synchronized wptr or on reset
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//---------------------------------------------------------------
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assign rempty_val = (rgraynext == rq2_wptr);
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always @(posedge rclk or negedge rrst_n)
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if (!rrst_n) rempty <= 1'b1;
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else rempty <= rempty_val;
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endmodule // rptr_empty
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