mirror of
https://github.com/openhwgroup/cvw
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73 lines
2.4 KiB
Systemverilog
73 lines
2.4 KiB
Systemverilog
///////////////////////////////////////////
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// fifo.sv
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//
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// Written: Clifford E Cummings 16 June 2005
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// Modified: james.stine@okstate.edu 19 February 2024
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//
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// Purpose: Asynchronous FIFO
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//
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// Documentation:
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fifo #(parameter DSIZE = 8,
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parameter ASIZE = 4)
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(rdata, wfull, rempty, wdata,
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winc, wclk, wrst_n, rinc, rclk, rrst_n);
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input logic [DSIZE-1:0] wdata;
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input logic winc;
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input logic wclk;
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input logic wrst_n;
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input logic rinc;
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input logic rclk;
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input logic rrst_n;
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output logic [DSIZE-1:0] rdata;
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output logic wfull;
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output logic rempty;
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logic [ASIZE-1:0] waddr, raddr;
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logic [ASIZE:0] wptr, rptr, wq2_rptr, rq2_wptr;
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sync_r2w sync_r2w (.wq2_rptr(wq2_rptr), .rptr(rptr),
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.wclk(wclk), .wrst_n(wrst_n));
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sync_w2r sync_w2r (.rq2_wptr(rq2_wptr), .wptr(wptr),
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.rclk(rclk), .rrst_n(rrst_n));
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fifomem #(DSIZE, ASIZE) fifomem (.rdata(rdata), .wdata(wdata),
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.waddr(waddr), .raddr(raddr),
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.wclken(winc), .wfull(wfull),
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.wclk(wclk));
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rptr_empty #(ASIZE) rptr_empty (.rempty(rempty), .raddr(raddr),
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.rptr(rptr), .rq2_wptr(rq2_wptr),
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.rinc(rinc), .rclk(rclk),
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.rrst_n(rrst_n));
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wptr_full #(ASIZE) wptr_full (.wfull(wfull), .waddr(waddr),
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.wptr(wptr), .wq2_rptr(wq2_rptr),
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.winc(winc), .wclk(wclk),
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.wrst_n(wrst_n));
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endmodule // fifo1
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