Ross Thompson 3f59ea6b6d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main		2022-10-04 17:38:49 -05:00
..
cache	Reordered the eviction and fetch in cache so it follows a more logical order.	2022-10-04 17:36:07 -05:00
ebu	Added logic to not implement the save/restore muxes for LSU in the EBU's controller input stage.	2022-09-29 18:37:34 -05:00
fpu	Adding start signals for integer divider to fdivsqrt	2022-09-29 16:30:25 -07:00
generic
hazard
ieu
ifu	Disable IFU bus access on TrapM.	2022-10-01 14:54:16 -05:00
lsu	addded renamed file	2022-10-04 17:37:05 +00:00
mmu
muldiv
ppa
privileged	Fixed a very subtle bug in the trap handler. It was possible to select the wrong cause if an interrupt was pending, but it was supressed by Committed and another exception triggered.	2022-10-02 16:21:21 -05:00
uncore	Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore.	2022-09-29 11:54:03 -05:00
wally	Added integer inputs and flags to divsqrt	2022-09-29 23:08:27 +00:00
sdc