Ross Thompson 44196af61a Have program which checks for sdc init and issues read, but read done is ... not correctly being read back by the software. The error is in how the sdc indicates busy.		2021-09-24 15:53:38 -05:00
..
adrdec.sv	Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.	2021-06-24 19:59:29 -04:00
adrdecs.sv	Have program which checks for sdc init and issues read, but read done is	2021-09-24 15:53:38 -05:00
decoder.sv	remove redundant decodes, fixed mmu logic ins/outs	2021-06-07 19:23:30 -04:00
hptw.sv	Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR	2021-09-03 10:26:38 -05:00
mmu.sv	partial dcache reorg.	2021-08-25 12:42:05 -05:00
pmachecker.sv	SDC to ABHLite interface partially done.	2021-09-24 10:45:09 -05:00
pmpadrdec.sv	Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's	2021-07-23 11:57:58 -05:00
pmpchecker.sv	Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's	2021-07-23 11:57:58 -05:00
priorityonehot.sv	Lint cleaning, riscv-arch-test testing	2021-09-09 11:05:12 -04:00
prioritythermometer.sv	Lint cleaning, riscv-arch-test testing	2021-09-09 11:05:12 -04:00
tlb.sv	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-21 16:39:07 -05:00
tlbcam.sv	Replaced .or with or_rows structural code in MMU read circuitry for synthesis.	2021-07-13 09:32:02 -04:00
tlbcamline.sv	Fixed TLB parameterization and valid bit flop to correctly do instr page faults	2021-07-21 14:44:43 -04:00
tlbcontrol.sv	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-07-21 16:44:32 -05:00
tlblru.sv	Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's	2021-07-23 11:57:58 -05:00
tlbmixer.sv	Broken.	2021-07-19 10:33:27 -05:00
tlbram.sv	Replaced .or with or_rows structural code in MMU read circuitry for synthesis.	2021-07-13 09:32:02 -04:00
tlbramline.sv	Eliminate reserved bits from TLB RAM	2021-07-08 17:35:00 -04:00