mirror of
https://github.com/openhwgroup/cvw
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f1107c5d7b
Added performance counters to individually track branches; jumps, jump register, jal, and jalr; return. jump and jump register are special cases of jal and jalr. Similarlly return is a special case of jalr. Also added counters to track if the branch direction was wrong, btb target wrong, or the ras target was wrong. Finally added one more counter to track if the BP incorrectly predicts a non-cfi instruction.
123 lines
4.1 KiB
Systemverilog
123 lines
4.1 KiB
Systemverilog
///////////////////////////////////////////
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// SRAM2P1R1W
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//
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// Written: Ross Thomposn
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// Email: ross1728@gmail.com
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// Created: February 15, 2021
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// Modified:
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//
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// Purpose: BTB model. Outputs type of instruction (currently 1 hot encoded. Probably want
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// to encode to reduce storage), valid, target PC.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module BTBPredictor
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#(parameter int Depth = 10
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)
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(input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, FlushF, FlushD, FlushE,
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input logic [`XLEN-1:0] LookUpPC,
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output logic [`XLEN-1:0] TargetPC,
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output logic [4:0] InstrClass,
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output logic Valid,
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// update
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input logic UpdateEN,
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input logic [`XLEN-1:0] UpdatePC,
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input logic [`XLEN-1:0] UpdateTarget,
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input logic [4:0] UpdateInstrClass,
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input logic UpdateInvalid
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);
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localparam TotalDepth = 2 ** Depth;
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logic [TotalDepth-1:0] ValidBits;
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logic [Depth-1:0] LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ;
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logic UpdateENQ;
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// hashing function for indexing the PC
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// We have Depth bits to index, but XLEN bits as the input.
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// bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
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// using compressed instructions. XOR bit 1 with the MSB of index.
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assign UpdatePCIndex = {UpdatePC[Depth+1] ^ UpdatePC[1], UpdatePC[Depth:2]};
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assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]};
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flopenr #(Depth) UpdatePCIndexReg(.clk(clk),
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.reset(reset),
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.en(~StallE),
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.d(UpdatePCIndex),
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.q(UpdatePCIndexQ));
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// The valid bit must be resetable.
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always_ff @ (posedge clk) begin
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if (reset) begin
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ValidBits <= #1 {TotalDepth{1'b0}};
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end else
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if (UpdateENQ) begin
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ValidBits[UpdatePCIndexQ] <= #1 ~ UpdateInvalid;
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end
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end
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assign Valid = ValidBits[LookUpPCIndexQ];
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/* -----\/----- EXCLUDED -----\/-----
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regfile2p1r1w #(10, 1) validMem(.clk(clk),
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.reset(reset),
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.RA1(LookUpPCIndexQ),
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.RD1(Valid),
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.REN1(1'b1),
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.WA1(UpdatePCIndexQ),
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.WD1(1'b1),
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.WEN1(UpdateEN));
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-----/\----- EXCLUDED -----/\----- */
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flopenr #(1) UpdateENReg(.clk(clk),
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.reset(reset),
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.en(~StallF),
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.d(UpdateEN),
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.q(UpdateENQ));
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flopenr #(Depth) LookupPCIndexReg(.clk(clk),
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.reset(reset),
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.en(~StallF),
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.d(LookUpPCIndex),
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.q(LookUpPCIndexQ));
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// the BTB contains the target address.
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// Another optimization may be using a PC relative address.
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// *** need to add forwarding.
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SRAM2P1R1W #(Depth, `XLEN+5) memory(.clk(clk),
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.reset(reset),
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.RA1(LookUpPCIndex),
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.RD1({{InstrClass, TargetPC}}),
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.REN1(~StallF),
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.WA1(UpdatePCIndex),
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.WD1({UpdateInstrClass, UpdateTarget}),
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.WEN1(UpdateEN),
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.BitWEN1({5'h1F, {`XLEN{1'b1}}})); // *** definitely not right.
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endmodule
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