mirror of
https://github.com/openhwgroup/cvw
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565 lines
28 KiB
Python
Executable File
565 lines
28 KiB
Python
Executable File
#!/usr/bin/env python3
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##################################
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#
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# regression-wally
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# David_Harris@Hmc.edu 25 January 2021
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# Modified by Jarred Allen <jaallen@g.hmc.edu> and many others
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#
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# Run a regression with multiple configurations in parallel and exit with
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# non-zero status code if an error happened, as well as printing human-readable
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# output.
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#
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##################################
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import sys,os,shutil
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import argparse
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import multiprocessing
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from collections import namedtuple
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from multiprocessing import Pool, TimeoutError
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##################################
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# Define lists of configurations and tests to run on each configuration
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##################################
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# The tests are a list with one element for each configuration
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# The element consists of the configuration name, a list of test suites to run,
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# optionally a string to pass to the simulator, and optionally a nonstandard grep string to check for success
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tests = [
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["rv32e", ["arch32e"]],
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["rv32i", ["arch32i"]],
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["rv32imc", ["arch32i", "arch32c", "arch32m", "wally32periph"]],
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["rv32gc", ["arch32f", "arch32d", "arch32f_fma", "arch32d_fma", "arch32f_divsqrt", "arch32d_divsqrt",
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"arch32i", "arch32priv", "arch32c", "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond",
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"arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "arch32zfh", "arch32zfh_fma",
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"arch32zfh_divsqrt", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "wally32priv", "wally32periph", "arch32zcb",
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"arch32zbkb", "arch32zbkc", "arch32zbkx", "arch32zknd", "arch32zkne", "arch32zknh"]],
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["rv64i", ["arch64i"]]
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]
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# Separate test for short buildroot run through OpenSBI UART output
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tests_buildrootshort = [
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["buildroot", ["buildroot"], [f"+INSTR_LIMIT=1400000"], # Instruction limit gets to first OpenSBI UART output
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"OpenSBI v", "buildroot_uart.out"]
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]
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# Separate test for full buildroot run
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tests_buildrootboot = [
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["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000"], # boot entire buildroot Linux to login prompt
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"WallyHostname login: ", "buildroot_uart.out"]
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]
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tests_buildrootbootlockstep = [
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["buildroot", ["buildroot"], [f"+INSTR_LIMIT=600000000 --lockstep"], # boot entire buildroot Linux to login prompt
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"WallyHostname login: ", "buildroot_uart.out"]
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]
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# Separate out floating-point tests for RV64 to speed up coverage
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tests64gc_nofp = [
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["rv64gc", ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb",
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"arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "wally64priv",
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"arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
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"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]] # add when working: "arch64zicboz"
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]
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tests64gc_fp = [
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["rv64gc", ["arch64f", "arch64d", "arch64zfh",
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"arch64f_fma", "arch64d_fma", "arch64zfh_fma",
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"arch64f_divsqrt", "arch64d_divsqrt", "arch64zfh_divsqrt",
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"arch64zfaf", "arch64zfad"]]
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]
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derivconfigtests = [
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# memory system
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["tlb2_rv32gc", ["wally32priv"]],
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["tlb16_rv32gc", ["wally32priv"]],
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["tlb2_rv64gc", ["wally64priv"]],
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["tlb16_rv64gc", ["wally64priv"]],
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["way_1_4096_512_rv32gc", ["arch32i"]],
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["way_2_4096_512_rv32gc", ["arch32i"]],
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["way_8_4096_512_rv32gc", ["arch32i"]],
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["way_4_2048_512_rv32gc", ["arch32i"]],
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["way_4_4096_256_rv32gc", ["arch32i"]],
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["way_1_4096_512_rv64gc", ["arch64i"]],
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["way_2_4096_512_rv64gc", ["arch64i"]],
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["way_8_4096_512_rv64gc", ["arch64i"]],
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["way_4_2048_512_rv64gc", ["arch64i"]],
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["way_4_4096_256_rv64gc", ["arch64i"]],
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["way_4_4096_1024_rv64gc", ["arch64i"]],
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["ram_0_0_rv64gc", ["ahb64"]],
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["ram_1_0_rv64gc", ["ahb64"]],
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["ram_1_1_rv64gc", ["ahb64"]],
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["ram_2_0_rv64gc", ["ahb64"]],
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["ram_2_1_rv64gc", ["ahb64"]],
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# RV32 cacheless designs will not work unless DTIM supports FLEN > XLEN. This support is not planned.
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# ["nodcache_rv32gc", ["ahb32"]],
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# ["nocache_rv32gc", ["ahb32"]],
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["noicache_rv32gc", ["ahb32"]],
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["noicache_rv64gc", ["ahb64"]],
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["nodcache_rv64gc", ["ahb64"]],
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["nocache_rv64gc", ["ahb64"]],
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# Atomic variants
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["zaamo_rv64gc", ["arch64i", "arch64a_amo"]],
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["zalrsc_rv64gc", ["arch64i", "wally64a_lrsc"]],
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["zaamo_rv32gc", ["arch32i", "arch32a_amo"]],
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["zalrsc_rv32gc", ["arch32i", "wally32a_lrsc"]],
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# Bit manipulation and crypto variants
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["zba_rv32gc", ["arch32i", "arch32zba"]],
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["zbb_rv32gc", ["arch32i", "arch32zbb"]],
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["zbc_rv32gc", ["arch32i", "arch32zbc"]],
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["zbs_rv32gc", ["arch32i", "arch32zbs"]],
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["zbkb_rv32gc", ["arch32i", "arch32zbkb"]],
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["zbkc_rv32gc", ["arch32i", "arch32zbkc"]],
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["zbkx_rv32gc", ["arch32i", "arch32zbkx"]],
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["zkne_rv32gc", ["arch32i", "arch32zkne"]],
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["zknd_rv32gc", ["arch32i", "arch32zknd"]],
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["zknh_rv32gc", ["arch32i", "arch32zknh"]],
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["zba_rv64gc", ["arch64i", "arch64zba"]],
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["zbb_rv64gc", ["arch64i", "arch64zbb"]],
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["zbc_rv64gc", ["arch64i", "arch64zbc"]],
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["zbs_rv64gc", ["arch64i", "arch64zbs"]],
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["zbkb_rv64gc", ["arch64i", "arch64zbkb"]],
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["zbkc_rv64gc", ["arch64i", "arch64zbkc"]],
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["zbkx_rv64gc", ["arch64i", "arch64zbkx"]],
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["zkne_rv64gc", ["arch64i", "arch64zkne"]],
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["zknd_rv64gc", ["arch64i", "arch64zknd"]],
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["zknh_rv64gc", ["arch64i", "arch64zknh"]],
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# No privilege modes variants
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["noS_rv32gc", ["arch32i", "arch32f", "arch32priv", "arch32c", "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond",
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"arch32zba", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "arch32zcb", "arch32zbkx", "arch32zknd"]],
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["noS_rv64gc", ["arch64i", "arch64f", "arch64priv", "arch64c", "arch64m", "arch64a_amo", "arch64zifencei", "arch64zicond",
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"arch64zba", "arch64zfaf", "arch64zfad", "wally64a_lrsc", "arch64zcb", "arch64zbkx", "arch64zknd"]],
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["noU_rv32gc", ["arch32i", "arch32f", "arch32priv", "arch32c", "arch32m", "arch32a_amo", "arch32zifencei", "arch32zicond",
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"arch32zba", "arch32zfaf", "arch32zfad", "wally32a_lrsc", "arch32zcb", "arch32zbkx", "arch32zknd"]],
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["noU_rv64gc", ["arch64i", "arch64f", "arch64priv", "arch64c", "arch64m", "arch64a_amo", "arch64zifencei", "arch64zicond",
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"arch64zba", "arch64zfaf", "arch64zfad", "wally64a_lrsc", "arch64zcb", "arch64zbkx", "arch64zknd"]],
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### add misaligned tests
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# fp/int divider permutations
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["div_2_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
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["div_2_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
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["div_2_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
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["div_2_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
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["div_2_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
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["div_2_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
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["div_4_1_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
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["div_4_1i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
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["div_4_2_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
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["div_4_2i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
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["div_4_4_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
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["div_4_4i_rv32gc", ["arch32f_divsqrt", "arch32d_divsqrt", "arch32m"]],
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["div_2_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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["div_2_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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["div_2_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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["div_2_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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["div_2_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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["div_2_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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["div_4_1_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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["div_4_1i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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["div_4_2_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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["div_4_2i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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["div_4_4_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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["div_4_4i_rv64gc", ["arch64f_divsqrt", "arch64d_divsqrt", "arch64m"]],
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# fpu permutations
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["f_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfaf"]],
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["fh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32zfaf"]],
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["fdh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32zfaf", "arch32zfad"]],
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["fdq_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32i", "arch32zfaf", "arch32zfad"]],
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["fdqh_rv32gc", ["arch32f", "arch32f_divsqrt", "arch32f_fma", "arch32d", "arch32d_divsqrt", "arch32d_fma", "arch32zfh", "arch32zfh_divsqrt", "arch32i", "arch32zfaf", "arch32zfad"]],
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["f_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfaf"]],
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["fh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf"]],
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["fdh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64zfaf", "arch64zfad"]],
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["fdq_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64i", "arch64zfaf", "arch64zfad"]],
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["fdqh_rv64gc", ["arch64f", "arch64f_divsqrt", "arch64f_fma", "arch64d", "arch64d_divsqrt", "arch64d_fma", "arch64zfh", "arch64zfh_divsqrt", "arch64i", "arch64zfaf", "arch64zfad"]], # "wally64q" when Q is supported again in riscof config file
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]
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bpredtests = [
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["nobpred_rv32gc", ["rv32i"]],
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["bpred_TWOBIT_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_12_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_14_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_16_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_6_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_8_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_10_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_12_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_14_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_TWOBIT_16_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_6_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_6_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_8_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_8_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_12_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_12_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_14_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_14_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_16_16_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_16_16_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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# btb
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["bpred_GSHARE_10_16_6_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_6_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_8_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_8_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_12_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_16_12_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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# ras
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["bpred_GSHARE_10_2_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_2_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_3_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_3_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_4_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_4_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_6_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_6_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_10_10_0_rv32gc", ["embench"], "-GPrintHPMCounters=1"],
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["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "-GPrintHPMCounters=1"]
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]
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# list of tests not supported by ImperasDV yet that should be waived during lockstep testing
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lockstepwaivers = [
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"WALLY-q-01.S_ref.elf", # Q extension is not supported by ImperasDV
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"WALLY-cbom-01.S_ref.elf" #, # cbom extension is not supported by ImperasDV because there is no cache model in ImperasDV
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]
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##################################
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# Data Types & Functions
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##################################
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TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr', 'grepfile'])
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# name: the name of this test configuration (used in printing human-readable
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# output and picking logfile names)
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# cmd: the command to run to test (should include the logfile as '{}', and
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# the command needs to write to that file)
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# grepstr: the string to grep through the log file for. The test succeeds iff
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# grep finds that string in the logfile (is used by grep, so it may
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# be any pattern grep accepts, see `man 1 grep` for more info).
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# grepfile: a string containing the location of the file to be searched for output
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class bcolors:
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HEADER = '\033[95m'
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OKBLUE = '\033[94m'
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OKCYAN = '\033[96m'
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OKGREEN = '\033[92m'
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WARNING = '\033[93m'
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FAIL = '\033[91m'
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ENDC = '\033[0m'
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BOLD = '\033[1m'
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UNDERLINE = '\033[4m'
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def addTests(tests, sim):
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sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
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for test in tests:
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config = test[0];
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suites = test[1];
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if (len(test) >= 3):
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args = " --args " + " ".join(test[2])
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else:
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args = ""
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if (len(test) >= 4):
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gs = test[3]
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else:
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gs = "All tests ran without failures"
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cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config
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for t in suites:
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sim_log = sim_logdir + config + "_" + t + ".log"
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if (len(test) >= 5):
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grepfile = sim_logdir + test[4]
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else:
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grepfile = sim_log
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tc = TestCase(
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name=t,
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variant=config,
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cmd=cmdPrefix + " " + t + args + " > " + sim_log,
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grepstr=gs,
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grepfile = grepfile)
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configs.append(tc)
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def addLockstepTestsByDir(dir, config, sim):
|
|
sim_logdir = WALLY+ "/sim/" + sim + "/logs/"
|
|
if (coverStr != ""): # use --fcov in place of --lockstep
|
|
cmdPrefix="wsim --sim " + sim + " " + coverStr + " " + config
|
|
else:
|
|
cmdPrefix="wsim --lockstep --sim " + sim + " " + config
|
|
if (os.path.isdir(dir)):
|
|
for dirpath, dirnames, filenames in os.walk(os.path.abspath(dir)):
|
|
for file in filenames:
|
|
if file.endswith(".elf"):
|
|
fullfile = os.path.join(dirpath, file)
|
|
fields = fullfile.rsplit('/', 3)
|
|
if (fields[2] == "ref"):
|
|
shortelf = fields[1] + "_" + fields[3]
|
|
else:
|
|
shortelf = fields[2] + "_" + fields[3]
|
|
if (shortelf in lockstepwaivers): # skip tests that itch bugs in ImperasDV
|
|
print(f"{bcolors.WARNING}Skipping waived test {shortelf}{bcolors.ENDC}")
|
|
continue
|
|
sim_log = sim_logdir + config + "_" + shortelf + ".log"
|
|
grepstring = ""
|
|
tc = TestCase(
|
|
name=file,
|
|
variant=config,
|
|
cmd=cmdPrefix + " " + fullfile + " > " + sim_log,
|
|
grepstr="Mismatches : 0",
|
|
grepfile = sim_log)
|
|
configs.append(tc)
|
|
else:
|
|
print("Error: Directory not found: " + dir)
|
|
exit(1)
|
|
|
|
def search_log_for_text(text, grepfile):
|
|
"""Search through the given log file for text, returning True if it is found or False if it is not"""
|
|
grepwarn = "grep -H Warning: " + grepfile
|
|
os.system(grepwarn)
|
|
greperr = "grep -H Error: " + grepfile
|
|
os.system(greperr)
|
|
grepcmd = "grep -a -e '%s' '%s' > /dev/null" % (text, grepfile)
|
|
# print(" search_log_for_text invoking %s" % grepcmd)
|
|
return os.system(grepcmd) == 0
|
|
|
|
def run_test_case(config):
|
|
"""Run the given test case, and return 0 if the test suceeds and 1 if it fails"""
|
|
grepfile = config.grepfile
|
|
cmd = config.cmd
|
|
os.chdir(regressionDir)
|
|
# print(" run_test_case invoking %s" % cmd)
|
|
os.system(cmd)
|
|
if search_log_for_text(config.grepstr, grepfile):
|
|
# print(f"{bcolors.OKGREEN}%s_%s: Success{bcolors.ENDC}" % (config.variant, config.name))
|
|
print(f"{bcolors.OKGREEN}%s: Success{bcolors.ENDC}" % (config.cmd))
|
|
return 0
|
|
else:
|
|
print(f"{bcolors.FAIL}%s: Failures detected in output{bcolors.ENDC}" % (config.cmd))
|
|
print(" Check %s" % grepfile)
|
|
return 1
|
|
|
|
##################################
|
|
# Main body
|
|
##################################
|
|
|
|
|
|
WALLY = os.environ.get('WALLY')
|
|
regressionDir = WALLY + '/sim'
|
|
os.chdir(regressionDir)
|
|
|
|
coveragesim = "questa" # Questa is required for code/functional coverage
|
|
#defaultsim = "questa" # Default simulator for all other tests; change to Verilator when flow is ready
|
|
defaultsim = "verilator" # Default simulator for all other tests
|
|
|
|
parser = argparse.ArgumentParser()
|
|
parser.add_argument("--ccov", help="Code Coverage", action="store_true")
|
|
parser.add_argument("--fcov", help="Functional Coverage", action="store_true")
|
|
parser.add_argument("--fcovrvvi", help="Functional Coverage RVVI", action="store_true")
|
|
parser.add_argument("--nightly", help="Run large nightly regression", action="store_true")
|
|
parser.add_argument("--buildroot", help="Include Buildroot Linux boot test (takes many hours, done along with --nightly)", action="store_true")
|
|
parser.add_argument("--testfloat", help="Include Testfloat floating-point unit tests", action="store_true")
|
|
parser.add_argument("--fp", help="Include floating-point tests in coverage (slower runtime)", action="store_true")
|
|
args = parser.parse_args()
|
|
|
|
if (args.nightly):
|
|
nightMode = "--nightly";
|
|
sims = ["questa", "verilator", "vcs"] # exercise all simulators; can omit a sim if no license is available
|
|
# sims = ["questa", "verilator"] # exercise all simulators; can omit a sim if no license is available
|
|
else:
|
|
nightMode = ""
|
|
sims = [defaultsim]
|
|
|
|
if (args.ccov): # only run RV64GC tests in coverage mode
|
|
coverStr = '--ccov'
|
|
elif (args.fcov): # only run RV64GC tests in lockstep in coverage mode
|
|
coverStr = '--fcov'
|
|
elif (args.fcovrvvi): # only run RV64GC tests in rvvi coverage mode
|
|
coverStr = '--fcovrvvi'
|
|
else:
|
|
coverStr = ''
|
|
|
|
|
|
# Run Lint
|
|
configs = [
|
|
TestCase(
|
|
name="lints",
|
|
variant="all",
|
|
cmd="lint-wally " + nightMode + " | tee " + WALLY + "/sim/verilator/logs/all_lints.log",
|
|
grepstr="lints run with no errors or warnings",
|
|
grepfile = WALLY + "/sim/verilator/logs/all_lints.log")
|
|
]
|
|
|
|
|
|
|
|
# run full buildroot boot simulation (slow) if buildroot flag is set. Start it early to overlap with other tests
|
|
if (args.buildroot):
|
|
# addTests(tests_buildrootboot, defaultsim) # non-lockstep with Verilator runs in about 2 hours
|
|
addTests(tests_buildrootbootlockstep, "questa") # lockstep with Questa and ImperasDV runs overnight
|
|
|
|
if (args.ccov): # only run RV64GC tests on Questa in code coverage mode
|
|
addTests(tests64gc_nofp, coveragesim)
|
|
if (args.fp):
|
|
addTests(tests64gc_fp, coveragesim)
|
|
elif (args.fcov): # only run RV64GC tests on Questa in lockstep in functional coverage mode
|
|
addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv32/", "rv32gc", coveragesim)
|
|
# addLockstepTestsByDir(WALLY+"/addins/cvw-arch-verif/tests/rv64/I", "rv64gc", coveragesim)
|
|
elif (args.fcovrvvi): # only run RV64GC tests on Questa in rvvi coverage mode
|
|
addTests(tests64gc_nofp, coveragesim)
|
|
if (args.fp):
|
|
addTests(tests64gc_fp, coveragesim)
|
|
else:
|
|
for sim in sims:
|
|
if (not (args.buildroot and sim == defaultsim)): # skip short buildroot sim if running long one
|
|
addTests(tests_buildrootshort, sim)
|
|
addTests(tests, sim)
|
|
addTests(tests64gc_nofp, sim)
|
|
addTests(tests64gc_fp, sim)
|
|
|
|
# run derivative configurations and lockstep tests in nightly regression
|
|
if (args.nightly):
|
|
addLockstepTestsByDir(WALLY+"/tests/coverage", "rv64gc", "questa")
|
|
addLockstepTestsByDir(WALLY+"/tests/riscof/work/wally-riscv-arch-test/rv64i_m", "rv64gc", "questa")
|
|
addTests(derivconfigtests, defaultsim)
|
|
|
|
# testfloat tests
|
|
if (args.testfloat): # for testfloat alone, just run testfloat tests
|
|
configs = []
|
|
if (args.testfloat or args.nightly): # for nightly, run testfloat along with others
|
|
testfloatsim = "questa" # change to Verilator when Issue #707 about testfloat not running Verilator is resolved
|
|
testfloatconfigs = ["fdqh_ieee_rv64gc", "fdq_ieee_rv64gc", "fdh_ieee_rv64gc", "fd_ieee_rv64gc", "fh_ieee_rv64gc", "f_ieee_rv64gc", "fdqh_ieee_rv32gc", "f_ieee_rv32gc"]
|
|
for config in testfloatconfigs:
|
|
tests = ["div", "sqrt", "add", "sub", "mul", "cvtint", "cvtfp", "fma", "cmp"]
|
|
if ("f_" in config):
|
|
tests.remove("cvtfp")
|
|
for test in tests:
|
|
sim_log = WALLY + "/sim/" + testfloatsim + "/logs/"+config+"_"+test+".log"
|
|
tc = TestCase(
|
|
name=test,
|
|
variant=config,
|
|
cmd="wsim --tb testbench_fp --sim " + testfloatsim + " " + config + " " + test + " > " + sim_log,
|
|
grepstr="All Tests completed with 0 errors",
|
|
grepfile = sim_log)
|
|
configs.append(tc)
|
|
|
|
|
|
testfloatdivconfigs = [
|
|
"fdh_ieee_div_2_1_rv32gc", "fdh_ieee_div_2_1_rv64gc", "fdh_ieee_div_2_2_rv32gc",
|
|
"fdh_ieee_div_2_2_rv64gc", "fdh_ieee_div_2_4_rv32gc", "fdh_ieee_div_2_4_rv64gc",
|
|
"fdh_ieee_div_4_1_rv32gc", "fdh_ieee_div_4_1_rv64gc", "fdh_ieee_div_4_2_rv32gc",
|
|
"fdh_ieee_div_4_2_rv64gc", "fdh_ieee_div_4_4_rv32gc", "fdh_ieee_div_4_4_rv64gc",
|
|
"fd_ieee_div_2_1_rv32gc", "fd_ieee_div_2_1_rv64gc", "fd_ieee_div_2_2_rv32gc",
|
|
"fd_ieee_div_2_2_rv64gc", "fd_ieee_div_2_4_rv32gc", "fd_ieee_div_2_4_rv64gc",
|
|
"fd_ieee_div_4_1_rv32gc", "fd_ieee_div_4_1_rv64gc", "fd_ieee_div_4_2_rv32gc",
|
|
"fd_ieee_div_4_2_rv64gc", "fd_ieee_div_4_4_rv32gc", "fd_ieee_div_4_4_rv64gc",
|
|
"fdqh_ieee_div_2_1_rv32gc", "fdqh_ieee_div_2_1_rv64gc", "fdqh_ieee_div_2_2_rv32gc",
|
|
"fdqh_ieee_div_2_2_rv64gc", "fdqh_ieee_div_2_4_rv32gc", "fdqh_ieee_div_2_4_rv64gc",
|
|
"fdqh_ieee_div_4_1_rv32gc", "fdqh_ieee_div_4_1_rv64gc", "fdqh_ieee_div_4_2_rv32gc",
|
|
"fdqh_ieee_div_4_2_rv64gc", "fdqh_ieee_div_4_4_rv32gc", "fdqh_ieee_div_4_4_rv64gc",
|
|
"fdq_ieee_div_2_1_rv32gc", "fdq_ieee_div_2_1_rv64gc", "fdq_ieee_div_2_2_rv32gc",
|
|
"fdq_ieee_div_2_2_rv64gc", "fdq_ieee_div_2_4_rv32gc", "fdq_ieee_div_2_4_rv64gc",
|
|
"fdq_ieee_div_4_1_rv32gc", "fdq_ieee_div_4_1_rv64gc", "fdq_ieee_div_4_2_rv32gc",
|
|
"fdq_ieee_div_4_2_rv64gc", "fdq_ieee_div_4_4_rv32gc", "fdq_ieee_div_4_4_rv64gc",
|
|
"fh_ieee_div_2_1_rv32gc", "fh_ieee_div_2_1_rv64gc", "fh_ieee_div_2_2_rv32gc",
|
|
"fh_ieee_div_2_2_rv64gc", "fh_ieee_div_2_4_rv32gc", "fh_ieee_div_2_4_rv64gc",
|
|
"fh_ieee_div_4_1_rv32gc", "fh_ieee_div_4_1_rv64gc", "fh_ieee_div_4_2_rv32gc",
|
|
"fh_ieee_div_4_2_rv64gc", "fh_ieee_div_4_4_rv32gc", "fh_ieee_div_4_4_rv64gc",
|
|
"f_ieee_div_2_1_rv32gc", "f_ieee_div_2_1_rv64gc", "f_ieee_div_2_2_rv32gc",
|
|
"f_ieee_div_2_2_rv64gc", "f_ieee_div_2_4_rv32gc", "f_ieee_div_2_4_rv64gc",
|
|
"f_ieee_div_4_1_rv32gc", "f_ieee_div_4_1_rv64gc", "f_ieee_div_4_2_rv32gc",
|
|
"f_ieee_div_4_2_rv64gc", "f_ieee_div_4_4_rv32gc", "f_ieee_div_4_4_rv64gc"
|
|
]
|
|
for config in testfloatdivconfigs:
|
|
# div test case
|
|
tests = ["div", "sqrt"]
|
|
if ("ieee" in config):
|
|
tests.append("cvtint")
|
|
tests.append("cvtfp")
|
|
if ("f_" in config):
|
|
tests.remove("cvtfp")
|
|
for test in tests:
|
|
sim_log = WALLY + "/sim/questa/logs/"+config+"_"+test+".log"
|
|
tc = TestCase(
|
|
name=test,
|
|
variant=config,
|
|
cmd="wsim --tb testbench_fp " + config + " " + test + " > " + sim_log,
|
|
grepstr="All Tests completed with 0 errors",
|
|
grepfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log")
|
|
configs.append(tc)
|
|
|
|
|
|
def main():
|
|
"""Run the tests and count the failures"""
|
|
global configs, args
|
|
os.chdir(regressionDir)
|
|
dirs = ["questa/logs", "questa/wkdir", "verilator/logs", "verilator/wkdir", "vcs/logs", "vcs/wkdir"]
|
|
for d in dirs:
|
|
try:
|
|
os.system('rm -rf %s' % d)
|
|
os.mkdir(d)
|
|
except:
|
|
pass
|
|
if args.ccov:
|
|
TIMEOUT_DUR = 20*60 # seconds
|
|
os.system('rm -f questa/cov/*.ucdb')
|
|
elif args.fcovrvvi:
|
|
TIMEOUT_DUR = 20*60
|
|
os.system('rm -f questa/fcovrvvi_ucdb/* questa/fcovrvvi_logs/* questa/fcovrvvi/*')
|
|
elif args.fcov:
|
|
TIMEOUT_DUR = 1*60
|
|
os.system('rm -f questa/fcov_ucdb/* questa/fcov_logs/* questa/fcov/*')
|
|
elif args.buildroot:
|
|
TIMEOUT_DUR = 60*1440 # 1 day
|
|
elif args.testfloat:
|
|
TIMEOUT_DUR = 30*60 # seconds
|
|
elif args.nightly:
|
|
TIMEOUT_DUR = 30*60 # seconds
|
|
else:
|
|
TIMEOUT_DUR = 10*60 # seconds
|
|
|
|
# Scale the number of concurrent processes to the number of test cases, but
|
|
# max out at a limited number of concurrent processes to not overwhelm the system
|
|
# right now fcov, ccov, nightly all use Imperas
|
|
if (args.ccov or args.fcov or args.nightly):
|
|
ImperasDVLicenseCount = 8 # limit number of concurrent processes to avoid overloading ImperasDV licenses
|
|
else:
|
|
ImperasDVLicenseCount = 10000 # effectively no license limit for non-lockstep tests
|
|
with Pool(processes=min(len(configs),multiprocessing.cpu_count(), ImperasDVLicenseCount)) as pool:
|
|
num_fail = 0
|
|
results = {}
|
|
for config in configs:
|
|
results[config] = pool.apply_async(run_test_case,(config,))
|
|
for (config,result) in results.items():
|
|
try:
|
|
num_fail+=result.get(timeout=TIMEOUT_DUR)
|
|
except TimeoutError:
|
|
num_fail+=1
|
|
print(f"{bcolors.FAIL}%s_%s: Timeout - runtime exceeded %d seconds{bcolors.ENDC}" % (config.variant, config.name, TIMEOUT_DUR))
|
|
|
|
# Coverage report
|
|
if args.ccov:
|
|
os.system('make QuestaCodeCoverage')
|
|
if args.fcov:
|
|
#os.system('make QuestaFunctCoverage')
|
|
os.system('make -f '+WALLY+'/addins/cvw-arch-verif/Makefile merge')
|
|
if args.fcovrvvi:
|
|
os.system('make QuestaFunctCoverageRvvi')
|
|
# Count the number of failures
|
|
if num_fail:
|
|
print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
|
|
else:
|
|
print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}")
|
|
return num_fail
|
|
|
|
if __name__ == '__main__':
|
|
exit(main())
|