mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
84 lines
3.2 KiB
Systemverilog
84 lines
3.2 KiB
Systemverilog
module unpacking (
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input logic [63:0] X, Y, Z,
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input logic FmtE,
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input logic [2:0] FOpCtrlE,
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output logic XSgnE, YSgnE, ZSgnE,
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output logic [10:0] XExpE, YExpE, ZExpE,
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output logic [52:0] XManE, YManE, ZManE,
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output logic XNormE,
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output logic XNaNE, YNaNE, ZNaNE,
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output logic XSNaNE, YSNaNE, ZSNaNE,
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output logic XDenormE, YDenormE, ZDenormE,
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output logic XZeroE, YZeroE, ZZeroE,
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output logic [10:0] BiasE,
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output logic XInfE, YInfE, ZInfE,
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output logic XExpMaxE
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);
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logic [51:0] XFracE, YFracE, ZFracE;
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logic XExpNonzero, YExpNonzero, ZExpNonzero;
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logic XFracZero, YFracZero, ZFracZero; // input fraction zero
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logic XExpZero, YExpZero, ZExpZero; // input exponent zero
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logic YExpMaxE, ZExpMaxE; // input exponent all 1s
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assign XSgnE = FmtE ? X[63] : X[31];
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assign YSgnE = FmtE ? Y[63] : Y[31];
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assign ZSgnE = FmtE ? Z[63] : Z[31];
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assign XExpE = FmtE ? X[62:52] : {3'b0, X[30:23]};//{X[30], {3{~X[30]&~XExpZero|XExpMaxE}}, X[29:23]};
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assign YExpE = FmtE ? Y[62:52] : {3'b0, Y[30:23]};//{Y[30], {3{~Y[30]&~YExpZero|YExpMaxE}}, Y[29:23]};
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assign ZExpE = FmtE ? Z[62:52] : {3'b0, Z[30:23]};//{Z[30], {3{~Z[30]&~ZExpZero|ZExpMaxE}}, Z[29:23]};
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/* assign XExpE = FmtE ? X[62:52] : {3'b0, X[30:23]}; // *** maybe convert to full number of bits here?
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assign YExpE = FmtE ? Y[62:52] : {3'b0, Y[30:23]};
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assign ZExpE = FmtE ? Z[62:52] : {3'b0, Z[30:23]};*/
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assign XFracE = FmtE ? X[51:0] : {X[22:0], 29'b0};
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assign YFracE = FmtE ? Y[51:0] : {Y[22:0], 29'b0};
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assign ZFracE = FmtE ? Z[51:0] : {Z[22:0], 29'b0};
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assign XExpNonzero = FmtE ? |X[62:52] : |X[30:23];
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assign YExpNonzero = FmtE ? |Y[62:52] : |Y[30:23];
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assign ZExpNonzero = FmtE ? |Z[62:52] : |Z[30:23];
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assign XExpZero = ~XExpNonzero;
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assign YExpZero = ~YExpNonzero;
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assign ZExpZero = ~ZExpNonzero;
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assign XFracZero = ~|XFracE;
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assign YFracZero = ~|YFracE;
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assign ZFracZero = ~|ZFracE;
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assign XManE = {XExpNonzero, XFracE};
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assign YManE = {YExpNonzero, YFracE};
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assign ZManE = {ZExpNonzero, ZFracE};
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assign XExpMaxE = FmtE ? &X[62:52] : &X[30:23];
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assign YExpMaxE = FmtE ? &Y[62:52] : &Y[30:23];
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assign ZExpMaxE = FmtE ? &Z[62:52] : &Z[30:23];
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assign XNormE = ~(XExpMaxE|XExpZero);
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assign XNaNE = XExpMaxE & ~XFracZero;
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assign YNaNE = YExpMaxE & ~YFracZero;
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assign ZNaNE = ZExpMaxE & ~ZFracZero;
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assign XSNaNE = XNaNE&~XFracE[51];
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assign YSNaNE = YNaNE&~YFracE[51];
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assign ZSNaNE = ZNaNE&~ZFracE[51];
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assign XDenormE = XExpZero & ~XFracZero;
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assign YDenormE = YExpZero & ~YFracZero;
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assign ZDenormE = ZExpZero & ~ZFracZero;
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assign XInfE = XExpMaxE & XFracZero;
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assign YInfE = YExpMaxE & YFracZero;
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assign ZInfE = ZExpMaxE & ZFracZero;
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assign XZeroE = XExpZero & XFracZero;
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assign YZeroE = YExpZero & YFracZero;
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assign ZZeroE = ZExpZero & ZFracZero;
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assign BiasE = FmtE ? 13'h3ff : 13'h7f; // *** is it better to convert to full precision exponents so bias isn't needed?
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// assign BiasE = 13'h3ff; // always use 1023 because exponents are unpacked to double precision
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endmodule |