mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
195 lines
6.1 KiB
Python
195 lines
6.1 KiB
Python
#!/usr/bin/python3
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##################################
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# testgen-ADD-SUB.py
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#
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# ushakya@hmc.edu & dottolia@hmc.edu 14 Feb 2021
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#
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# Generate directed and random test vectors for RISC-V Design Validation.
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##################################
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##################################
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# libraries
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##################################
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from datetime import datetime
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from random import randint
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from random import seed
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from random import getrandbits
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##################################
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# functions
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##################################
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# def computeExpected(a, b, test):
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# if (test == "ADD"):
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# return a + b
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# elif (test == "SUB"):
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# return a - b
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# else:
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# die("bad test name ", test)
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# # exit(1)
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def randRegs():
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reg1 = randint(1,31)
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reg2 = randint(1,31)
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reg3 = randint(1,31)
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if (reg1 == 6 or reg2 == 6 or reg3 == 6 or reg1 == reg2):
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return randRegs()
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else:
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return reg1, reg2, reg3
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def writeVector(a, b, storecmd):
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global testnum
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#expected = computeExpected(a, b, test)
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#expected = expected % 2**xlen # drop carry if necessary
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#if (expected < 0): # take twos complement
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# expected = 2**xlen + expected
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csr = "mscratch"
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reg1, reg2, reg3 = randRegs()
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lines = "\n# Testcase " + str(testnum) + ": " + csr + "\n"
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lines = lines + "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
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lines = lines + "li x" + str(reg2) + ", MASK_XLEN(0)\n"
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# Page 6 of unpriviledged spec
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# For both CSRRS and CSRRC, if rs1=x0, then the instruction will not write to the CSR at all, and so shall not cause any of the side effects
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expected = a
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if test == "csrrw":
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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elif test == "csrrs": # at some point, try writing a non-zero value first
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lines += "csrrw x0, " + csr + ", x0\n" # set csr to 0
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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elif test == "csrrc": # at some point, try writing a non-one value first
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allOnes = "0xFFFFFFFF" if xlen == 32 else "0xFFFFFFFFFFFFFFFF"
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lines += "li x" + str(reg1) + ", MASK_XLEN(" + allOnes + ")\n"
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lines += "csrrw x0, " + csr + ", x" + str(reg1) + "\n" # set csr to all ones
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lines += "li x" + str(reg1) + ", MASK_XLEN(" + formatstr.format(a) + ")\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", x" + str(reg1) + "\n"
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expected = a ^ 0xFFFFFFFF if xlen == 32 else a ^ 0xFFFFFFFFFFFFFFFF
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elif test == "csrrwi":
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a = a & 0x1F # imm is only 5 bits
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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expected = a
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elif test == "csrrsi": # at some point, try writing a non-zero value first
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a = a & 0x1F
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lines += "csrrw x0, " + csr + ", x0\n" # set csr to 0
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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expected = a
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elif test == "csrrci": # at some point, try writing a non-one value first
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a = a & 0x1F
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allOnes = "0xFFFFFFFF" if xlen == 32 else "0xFFFFFFFFFFFFFFFF"
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lines += "li x" + str(reg1) + ", MASK_XLEN(" + allOnes + ")\n"
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lines += "csrrw x0, " + csr + ", x" + str(reg1) + "\n" # set csr to all ones
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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lines += test + " x" + str(reg2) + ", " + csr + ", " + str(a) + "\n"
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expected = a ^ 0xFFFFFFFF if xlen == 32 else a ^ 0xFFFFFFFFFFFFFFFF
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lines += storecmd + " x" + str(reg2) + ", " + str(wordsize*testnum) + "(x6)\n"
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lines += "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg2) +", "+formatstr.format(expected)+")\n"
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f.write(lines)
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if (xlen == 32):
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line = formatrefstr.format(expected)+"\n"
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else:
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line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
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r.write(line)
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testnum = testnum+1
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##################################
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# main body
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##################################
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# change these to suite your tests
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# csrrw, csrrs, csrrc, csrrwi, csrrsi, csrrci
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tests = ["csrrw", "csrrs", "csrrc", "csrrwi", "csrrsi", "csrrci"]
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author = "ushakya@hmc.edu & dottolia@hmc.edu"
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xlens = [32, 64]
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numrand = 60;
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# setup
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seed(0xC365DDEB9173AB42) # make tests reproducible
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# generate files for each test
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for xlen in xlens:
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formatstrlen = str(int(xlen/4))
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formatstr = "0x{:0" + formatstrlen + "x}" # format as xlen-bit hexadecimal number
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formatrefstr = "{:08x}" # format as xlen-bit hexadecimal number with no leading 0x
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if (xlen == 32):
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storecmd = "sw"
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wordsize = 4
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else:
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storecmd = "sd"
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wordsize = 8
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for test in tests:
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corners = [
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0, 1, 2, 0x1E, 0x1F, 0xFF,
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0x624B3E976C52DD14 % 2**xlen, 2**(xlen-1)-2, 2**(xlen-1)-1,
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2**(xlen-1), 2**(xlen-1)+1, 0xC365DDEB9173AB42 % 2**xlen, 2**(xlen)-2, 2**(xlen)-1
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]
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imperaspath = "../../imperas-riscv-tests/riscv-test-suite/rv" + str(xlen) + "i/"
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basename = "WALLY-" + test.upper()
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fname = imperaspath + "src/" + basename + ".S"
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refname = imperaspath + "references/" + basename + ".reference_output"
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testnum = 0
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# print custom header part
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f = open(fname, "w")
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r = open(refname, "w")
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line = "///////////////////////////////////////////\n"
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f.write(line)
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lines="// "+fname+ "\n// " + author + "\n"
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f.write(lines)
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line ="// Created " + str(datetime.now())
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f.write(line)
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# insert generic header
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h = open("testgen_header.S", "r")
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for line in h:
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f.write(line)
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# print directed and random test vectors
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for a in corners:
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for b in corners:
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writeVector(a, b, storecmd)
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for i in range(0,numrand):
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a = getrandbits(xlen)
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b = getrandbits(xlen)
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writeVector(a, b, storecmd)
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# print footer
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h = open("testgen_footer.S", "r")
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for line in h:
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f.write(line)
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# Finish
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lines = ".fill " + str(testnum) + ", " + str(wordsize) + ", -1\n"
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lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
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f.write(lines)
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f.close()
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r.close()
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