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39 lines
1.6 KiB
Systemverilog
39 lines
1.6 KiB
Systemverilog
///////////////////////////////////////////
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// instrTrackerTB.sv
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module instrTrackerTB(
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input logic clk, reset, FlushE,
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input logic [31:0] InstrF, InstrD,
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input logic [31:0] InstrE, InstrM,
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input logic [31:0] InstrW,
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// output logic [31:0] InstrW,
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output string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// stage Instr to Writeback for visualization
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// flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
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instrNameDecTB fdec(InstrF, InstrFName);
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instrNameDecTB ddec(InstrD, InstrDName);
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instrNameDecTB edec(InstrE, InstrEName);
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instrNameDecTB mdec(InstrM, InstrMName);
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instrNameDecTB wdec(InstrW, InstrWName); // *** delete this because InstrW is deleted from IFU
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endmodule
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