mirror of
https://github.com/openhwgroup/cvw
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127 lines
3.4 KiB
Systemverilog
Executable File
127 lines
3.4 KiB
Systemverilog
Executable File
// testbench
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module testbench ();
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logic [63:0] op1;
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logic [63:0] op2;
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logic [2:0] FOpCtrlE;
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logic [2:0] FrmE;
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logic op_type;
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logic FmtE;
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logic OvEn;
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logic UnEn;
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logic XSgnE, YSgnE, ZSgnE;
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logic XSgnM, YSgnM;
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logic [10:0] XExpE, YExpE, ZExpE;
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logic [10:0] XExpM, YExpM, ZExpM;
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logic [52:0] XManE, YManE, ZManE;
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logic [52:0] XManM, YManM, ZManM;
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logic [10:0] BiasE;
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logic XNaNE, YNaNE, ZNaNE;
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logic XNaNM, YNaNM, ZNaNM;
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logic XSNaNE, YSNaNE, ZSNaNE;
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logic XSNaNM, YSNaNM, ZSNaNM;
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logic XDenormE, YDenormE, ZDenormE;
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logic XZeroE, YZeroE, ZZeroE;
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logic XZeroM, YZeroM, ZZeroM;
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logic XInfE, YInfE, ZInfE;
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logic XInfM, YInfM, ZInfM;
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logic XExpMaxE;
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logic XNormE;
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logic FDivBusyE;
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logic start;
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logic reset;
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logic XDenorm;
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logic YDenorm;
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logic [63:0] AS_Result;
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logic [4:0] Flags;
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logic Denorm;
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logic done;
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logic clk;
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logic [63:0] yexpected;
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logic [63:0] vectornum, errors; // bookkeeping variables
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logic [199:0] testvectors[50000:0]; // array of testvectors
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logic [7:0] flags_expected;
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integer handle3;
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integer desc3;
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integer desc4;
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// instantiate device under test
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unpacking unpacking(.X(op1), .Y(op2), .Z(64'h0), .FOpCtrlE, .FmtE,
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.XSgnE, .YSgnE, .ZSgnE, .XExpE, .YExpE, .ZExpE, .XManE, .YManE, .ZManE,
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.XNaNE, .YNaNE, .ZNaNE, .XSNaNE, .YSNaNE, .ZSNaNE, .XDenormE, .YDenormE, .ZDenormE,
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.XZeroE, .YZeroE, .ZZeroE, .BiasE, .XInfE, .YInfE, .ZInfE, .XExpMaxE, .XNormE);
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fpdiv fdivsqrt (.op1, .op2, .rm(FrmE[1:0]), .op_type(FOpCtrlE[0]),
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.reset, .clk, .start, .P(~FmtE), .OvEn(1'b0), .UnEn(1'b0),
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.XNaNQ(XNaNE), .YNaNQ(YNaNE), .XInfQ(XInfE), .YInfQ(YInfE), .XZeroQ(XZeroE), .YZeroQ(YZeroE),
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.FDivBusyE, .done(done), .AS_Result(AS_Result), .Flags(Flags));
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// current fpdivsqrt does not operation on denorms yet
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assign Denorm = XDenormE | YDenormE | Flags[3];
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// generate clock to sequence tests
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always
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begin
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clk = 1; # 5; clk = 0; # 5;
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end
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initial
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begin
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handle3 = $fopen("f64_div_rne.out");
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$readmemh("../testbench/fp/vectors/f64_div_rne.tv", testvectors);
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vectornum = 0; errors = 0;
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start = 1'b0;
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// reset
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reset = 1; #27; reset = 0;
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end
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initial
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begin
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desc3 = handle3;
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// Operation (if applicable)
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#0 op_type = 1'b0;
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// Precision (32-bit or 64-bit)
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#0 FmtE = 1'b1;
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// From fctrl logic to dictate operation
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#0 FOpCtrlE = 3'b000;
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// Rounding Mode
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#0 FrmE = 3'b000;
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// Trap masking (n/a for RISC-V)
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#0 OvEn = 1'b0;
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#0 UnEn = 1'b0;
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end
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always @(posedge clk)
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begin
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if (~reset)
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begin
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#0; {op1, op2, yexpected, flags_expected} = testvectors[vectornum];
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#50 start = 1'b1;
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repeat (2)
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@(posedge clk);
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// deassert start after 2 cycles
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start = 1'b0;
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repeat (10)
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@(posedge clk);
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$fdisplay(desc3, "%h_%h_%h_%b_%b | %h_%b", op1, op2, AS_Result, Flags, Denorm, yexpected, (AS_Result==yexpected));
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vectornum = vectornum + 1;
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if (vectornum == 40)
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$finish;
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if (testvectors[vectornum] === 200'bx) begin
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$display("%d tests completed", vectornum);
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$finish;
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end
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end // if (~reset)
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$display("%d vectors processed", vectornum);
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end // always @ (posedge clk)
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endmodule // tb
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