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38edbde966
CPU to $ is called LSURWM or IFURWF. CPU to Bus is called BusRW $ to Bus is called CacheBusRW.
90 lines
3.8 KiB
Systemverilog
90 lines
3.8 KiB
Systemverilog
///////////////////////////////////////////
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// ahbcacheinterface.sv
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//
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// Written: Ross Thompson ross1728@gmail.com August 29, 2022
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// Modified:
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//
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// Purpose: Cache/Bus data path.
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// Bus Side logic
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// register the fetch data from the next level of memory.
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// This register should be necessary for timing. There is no register in the uncore or
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// ahblite controller between the memories and this cache.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ahbcacheinterface #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
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(
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input logic HCLK, HRESETn,
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// bus interface
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input logic HREADY,
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input logic [`XLEN-1:0] HRDATA,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [1:0] HTRANS,
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output logic HWRITE,
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output logic [`PA_BITS-1:0] HADDR,
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output logic [LOGWPL-1:0] WordCount,
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// cache interface
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input logic [`PA_BITS-1:0] CacheBusAdr,
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input logic [1:0] CacheBusRW,
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output logic CacheBusAck,
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output logic [LINELEN-1:0] FetchBuffer,
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output logic SelUncachedAdr,
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// lsu/ifu interface
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input logic [`PA_BITS-1:0] PAdr,
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input logic [1:0] BusRW,
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input logic CPUBusy,
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input logic [2:0] Funct3,
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output logic SelBusWord,
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output logic BusStall,
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output logic BusCommitted);
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localparam integer WordCountThreshold = CACHE_ENABLED ? WORDSPERLINE - 1 : 0;
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logic [`PA_BITS-1:0] LocalHADDR;
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logic [LOGWPL-1:0] WordCountDelayed;
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logic CaptureEn;
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genvar index;
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for (index = 0; index < WORDSPERLINE; index++) begin:fetchbuffer
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logic [WORDSPERLINE-1:0] CaptureWord;
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assign CaptureWord[index] = CaptureEn & (index == WordCountDelayed);
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flopen #(`XLEN) fb(.clk(HCLK), .en(CaptureWord[index]), .d(HRDATA),
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.q(FetchBuffer[(index+1)*`XLEN-1:index*`XLEN]));
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end
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mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdr, SelUncachedAdr, LocalHADDR);
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assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR;
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mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
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buscachefsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) AHBBuscachefsm(
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.HCLK, .HRESETn, .BusRW, .CPUBusy, .BusCommitted, .BusStall, .CaptureEn, .SelBusWord,
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.CacheBusRW, .CacheBusAck, .SelUncachedAdr, .WordCount, .WordCountDelayed,
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.HREADY, .HTRANS, .HWRITE, .HBURST);
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endmodule
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