mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
37 lines
1.5 KiB
Plaintext
37 lines
1.5 KiB
Plaintext
wally/wallypipelinedcore.sv: logic PCM
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wally/wallypipelinedcore.sv: logic TrapM
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wally/wallypipelinedcore.sv: logic InstrValidM
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wally/wallypipelinedcore.sv: logic InstrM
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lsu/lsu.sv: logic IEUAdrM
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lsu/lsu.sv: logic MemRWM
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mmu/hptw.sv: logic SATP_REGW
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uncore/spi_apb.sv: logic ShiftIn
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uncore/spi_apb.sv: logic ReceiveShiftReg
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uncore/spi_apb.sv: logic SCLKenable
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uncore/spi_apb.sv: logic SampleEdge
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uncore/spi_apb.sv: logic Active
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uncore/spi_apb.sv: statetype state
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uncore/spi_apb.sv: typedef rsrstatetype
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uncore/spi_apb.sv: logic SPICLK
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uncore/spi_apb.sv: logic SPIOut
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uncore/spi_apb.sv: logic SPICS
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uncore/spi_apb.sv: logic SckMode
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uncore/spi_apb.sv: logic SckDiv
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uncore/spi_apb.sv: logic ShiftEdge
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uncore/spi_apb.sv: logic TransmitShiftRegLoadSingleCycle
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uncore/spi_apb.sv: logic TransmitShiftReg
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uncore/spi_apb.sv: logic TransmitData
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uncore/spi_apb.sv: logic ReceiveData
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uncore/spi_apb.sv: logic ReceiveShiftRegEndian
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uncore/spi_apb.sv: logic TransmitShiftReg
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uncore/spi_apb.sv: logic TransmitShift
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uncore/spi_apb.sv: logic ReceiveShiftFullDelay
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uncore/spi_apb.sv: logic TransmitShiftEmpty
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uncore/spi_apb.sv: logic ReceiveFIFOWriteFull
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uncore/spi_apb.sv: logic ReceiveFIFOReadIncrement
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uncore/spi_apb.sv: logic ReceiveFIFOReadEmpty
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uncore/spi_apb.sv: logic TransmitFIFOWriteIncrement
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uncore/spi_apb.sv: logic TransmitFIFOReadIncrement
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uncore/spi_apb.sv: logic TransmitFIFOWriteFull
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uncore/spi_apb.sv: logic TransmitFIFOReadEmpty
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