mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 13:04:28 +00:00
95 lines
3.9 KiB
Python
Executable File
95 lines
3.9 KiB
Python
Executable File
#!/usr/bin/env python3
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###########################################
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## rv64gc_CacheSim.py
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##
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## Written: lserafini@hmc.edu
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## Created: 11 April 2023
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## Modified: 12 April 2023
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## Modified: 10 August 2023, jcarlin@hmc.edu
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##
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## Purpose: Run the cache simulator on each rv64gc test suite in turn.
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##
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## A component of the CORE-V-WALLY configurable RISC-V project.
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## https://github.com/openhwgroup/cvw
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##
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## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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##
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## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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##
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## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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## except in compliance with the License, or, at your option, the Apache License version 2.0. You
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## may obtain a copy of the License at
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##
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## https:##solderpad.org/licenses/SHL-2.1/
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##
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## Unless required by applicable law or agreed to in writing, any work distributed under the
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## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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## either express or implied. See the License for the specific language governing permissions
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## and limitations under the License.
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################################################################################################
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import os
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import argparse
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import subprocess
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# NOTE: make sure testbench.sv has the ICache and DCache loggers enabled!
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# This does not check the test output for correctness, run regression for that.
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# Add -p or --perf to report the hit/miss ratio.
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# Add -d or --dist to report the distribution of loads, stores, and atomic ops.
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# These distributions may not add up to 100; this is because of flushes or invalidations.
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class bcolors:
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HEADER = '\033[95m'
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OKBLUE = '\033[94m'
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OKCYAN = '\033[96m'
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OKGREEN = '\033[92m'
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WARNING = '\033[93m'
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FAIL = '\033[91m'
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ENDC = '\033[0m'
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BOLD = '\033[1m'
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UNDERLINE = '\033[4m'
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tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zcb",
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"arch64zifencei", "arch64zicond", "arch64a_amo", "wally64a_lrsc", "wally64periph", "wally64priv",
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"arch64zbkb", "arch64zbkc", "arch64zbkx", "arch64zknd", "arch64zkne", "arch64zknh",
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"arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"]
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# arch64i is the most interesting case. Uncomment line below to run just that case
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# tests64gc = ["arch64i"]
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cachetypes = ["ICache", "DCache"]
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simdir = os.path.expandvars("$WALLY/sim")
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def main():
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parser = argparse.ArgumentParser(description="Runs the cache simulator on all rv64gc test suites")
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parser.add_argument('-p', "--perf", action='store_true', help="Report hit/miss ratio")
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parser.add_argument('-d', "--dist", action='store_true', help="Report distribution of operations")
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parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="verilator")
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args = parser.parse_args()
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simargs = "I_CACHE_ADDR_LOGGER=1\\\'b1 D_CACHE_ADDR_LOGGER=1\\\'b1"
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testcmd = "wsim --sim " + args.sim + " rv64gc {} --params \"" + simargs + "\" > /dev/null"
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cachecmd = "CacheSim.py 64 4 56 44 -f {}"
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mismatches = 0
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if args.perf:
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cachecmd += " -p"
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if args.dist:
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cachecmd += " -d"
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for test in tests64gc:
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print(f"{bcolors.HEADER}Commencing test", test+f":{bcolors.ENDC}")
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# remove wkdir to force recompile with logging enabled
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os.system("rm -rf " + simdir + "/" + args.sim + "/wkdir/rv64gc_" + test)
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os.system("rm -rf " + simdir + "/" + args.sim + "/*Cache.log")
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print(testcmd.format(test))
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os.system(testcmd.format(test))
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for cache in cachetypes:
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print(f"{bcolors.OKCYAN}Running the", cache, f"simulator.{bcolors.ENDC}")
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result = subprocess.run(cachecmd.format(args.sim+"/"+cache+".log"), shell=True)
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mismatches += result.returncode
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print()
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return mismatches
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if __name__ == '__main__':
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exit(main())
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