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https://github.com/openhwgroup/cvw
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49 lines
864 B
Makefile
49 lines
864 B
Makefile
# David_Harris@hmc.edu 2023
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# Top-level Makefile for CORE-V-Wally
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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SIM = ${WALLY}/sim
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all:
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make riscof
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make zsbl
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make testfloat
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# make verify
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make coverage
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# make benchmarks
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# riscof builds the riscv-arch-test and wally-riscv-arch-test suites
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riscof:
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make -C sim
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testfloat:
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cd ${WALLY}/addins/SoftFloat-3e/build/Linux-x86_64-GCC; make
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cd ${WALLY}/addins/TestFloat-3e/build/Linux-x86_64-GCC; make
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cd ${WALLY}/tests/fp; ./create_all_vectors.sh
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zsbl:
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$(MAKE) -C ${WALLY}/fpga/zsbl
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verify:
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cd ${SIM}; ./regression-wally
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cd ${SIM}/sim; ./sim-testfloat-batch all
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make imperasdv
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benchmarks:
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make coremark
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make embench
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coremark:
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cd ${WALLY}/benchmarks/coremark; make; make run
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embench:
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cd ${WALLY}/benchmarks/embench; make; make run
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coverage:
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make -C tests/coverage
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clean:
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make clean -C sim
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