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cvw/wally-pipelined/config
History
Ross Thompson abce241f68 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
2021-07-16 14:21:09 -05:00
..
buildroot Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0 2021-07-05 20:35:31 -04:00
busybear Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0 2021-07-05 20:35:31 -04:00
coremark Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00
coremark_bare Updated MISA defining as well as porting sizes for peripherals (34 to 56) 2021-07-07 02:37:09 -04:00
coremark-64i Switched to array notation for pmpchecker 2021-07-04 10:51:56 -04:00
rv32ic Also changed the shadow ram's dcache copy widths. 2021-07-16 14:21:09 -05:00
rv32icfd Fixed lint warning 2021-07-14 21:24:48 -04:00
rv64BP Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00
rv64ic Updated the config so the tim has a bigger range. 2021-07-16 12:35:00 -05:00
rv64icfd Fixed lint warning 2021-07-14 21:24:48 -04:00
rv64imc Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0 2021-07-05 20:35:31 -04:00
shared Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00