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86 lines
3.2 KiB
Systemverilog
86 lines
3.2 KiB
Systemverilog
///////////////////////////////////////////
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// alu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: RISC-V Arithmetic/Logic Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module alu #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B,
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input logic [2:0] ALUControl,
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input logic [2:0] Funct3,
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output logic [WIDTH-1:0] Result,
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output logic [WIDTH-1:0] Sum);
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logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult;
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logic Carry, Neg;
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logic LT, LTU;
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logic W64, SubArith, ALUOp;
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logic Asign, Bsign;
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// Extract control signals
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// W64 indicates RV64 W-suffix instructions acting on lower 32-bit word
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// SubArith indicates subtraction or arithmetic right shift
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// ALUOp = 0 for address generation addition or 1 for regular ALU
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assign {W64, SubArith, ALUOp} = ALUControl;
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// addition
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assign CondInvB = SubArith ? ~B : B;
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assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith};
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// Shifts
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shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift));
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// condition code flags based on subtract output Sum = A-B
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// Overflow occurs when the numbers being subtracted have the opposite sign
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// and the result has the opposite sign of A
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assign Neg = Sum[WIDTH-1];
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assign Asign = A[WIDTH-1];
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assign Bsign = B[WIDTH-1];
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assign LT = Asign & ~Bsign | Asign & Neg | ~Bsign & Neg; // simplified from Overflow = Asign & Bsign & Asign & Neg; LT = Neg ^ Overflow
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assign LTU = ~Carry;
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// SLT
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assign SLT = {{(WIDTH-1){1'b0}}, LT};
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assign SLTU = {{(WIDTH-1){1'b0}}, LTU};
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// Select appropriate ALU Result
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always_comb
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if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0
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else casez (Funct3) // Otherwise check Funct3
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3'b000: FullResult = Sum; // add or sub
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3'b?01: FullResult = Shift; // sll, sra, or srl
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3'b010: FullResult = SLT; // slt
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3'b011: FullResult = SLTU; // sltu
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3'b100: FullResult = A ^ B; // xor
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3'b110: FullResult = A | B; // or
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3'b111: FullResult = A & B; // and
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endcase
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// support W-type RV64I ADDW/SUBW/ADDIW/Shifts that sign-extend 32-bit result to 64 bits
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if (WIDTH==64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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else assign Result = FullResult;
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endmodule
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