mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-24 05:24:49 +00:00
479 lines
14 KiB
ArmAsm
479 lines
14 KiB
ArmAsm
///////////////////////////////////////////
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// tlbmisc.S
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//
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// Written David_Harris@hmc.edu 1/1/24
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//
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// Purpose: Test coverage for other TLB issues
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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# run-elf.bash find this in project description
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main:
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li t5, 0x1
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slli t5, t5, 62
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ori t5, t5, 0xF0
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csrs menvcfg, t5 # menvcfg.PBMTE = 1, CBZE, CBCFE, CBIE all 1
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# store ret instruction in case we jump to an address mapping to 80000000
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li t0, 0x80000000
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li t5, 0x8082 # return instruction opcode
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sw t5, 0(t0)
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fence.i
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# Test not being able to write illegal SATP mode
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li t5, 0xA000000000080010
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csrw satp, t5
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# Page table root address at 0x80010000; SV48
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li t5, 0x9000000000080010
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csrw satp, t5
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# sfence.vma x0, x0
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# switch to supervisor mode
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li a0, 1
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ecall
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# Instruction fetch from misaligned pages
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jal changetoipfhandler # set up trap handler to return from instruction page fault if necessary
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li t0, 0x8000000000
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jalr ra, t0 # jump misaligned terapage
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li t0, 0x00000000
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jalr ra, t0 # jump to misaligned gigapage
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li t0, 0x80200000
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jalr ra, t0 # jump to misaligned megapage
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li t0, 0x7FFFFFFF80000000
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jalr ra, t0 # jump to page with UpperBitsUnequal
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li t0, 0x0000000080C00000
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jalr ra, t0 # jump to page with bad reserved bits 60:54 in PTE
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# test with ENVCFG_ADUE = 1: switch to machine mode, set ADUE, access page with A=0, clear ADUE,
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li a0, 3
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ecall # switch to machine mode
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li t0, 1
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slli t0, t0, 61
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csrs menvcfg, t0 # set menvcfg.ADUE
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li a0, 1
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ecall # switch back to supervisor mode
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li t0, 0x0000000080E00000
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jalr ra, t0 # jump to page without accessed bit yet set
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li a0, 3
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ecall # switch to machine mode
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li t0, 1
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slli t0, t0, 61
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csrc menvcfg, t0 # clear menvcfg.ADUE
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li a0, 1
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ecall # switch back to supervisor mode
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# exercise malformed PBMT pages
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# page has PBMT = 3 (reserved)
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li t0, 0x80400000
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lw t1, 0(t0) # read from page
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sw t1, 0(t0) # write to page
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jalr ra, t0 # jump to page
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# AMO at page has PBMT = 2 or 1 (uncached)
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li t0, 0x80401000
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li t1, 10
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amoadd.w t1, t1, (t0)
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la t2, SpecialPage
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li t0, 0x200000000 # an address to a specific 1 GiB page
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j ConcurrentICacheMissDTLBMiss
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.align 6
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ConcurrentICacheMissDTLBMiss:
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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lw t1, 0(t0)
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# write a cacheline length (512 bits) to memory in uncached region
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li t0, 0x80401000
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cbo.zero (t0)
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# Nonleaf PTE has PBMT != 0 causes a page fault during page walking. H
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li t0, 0x80600000
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lw t1, 0(t0) # read from page
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sw t1, 0(t0) # write to page
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jalr ra, t0 # jump to page
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# jump to address for TLB miss to trigger HPTW to make access with DisableTranslation = 1, Translate = 0
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li t0, 0x80805000
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jalr ra, t0
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li t0, 0x80807000 # again, triggering setting access bit
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jalr ra, t0
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# atomic access to uncachable memory
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#li t0, 0x80806000
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#sd zero, 0(t0)
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#amoadd.w t1, t0, (t0)
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# Good PBMT with menvcfg.PBMTE = 0
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li a0, 3
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ecall # switch to machine mode
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li t5, 0x1
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slli t5, t5, 62
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csrc menvcfg, t5 # menvcfg.PBMTE = 0
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li a0, 1
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ecall # switch back to supervisor mode
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li t0, 0x80806000
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jalr ra, t0 # jump to page to exercise ITLB with PBMT !=0 when ENVCFG_PMTE=0
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# Load and AMO operation on page table entry that causes access fault
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li t0, 0x81000000
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lw t1, 0(t0)
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sfence.vma
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amoadd.w t0, t0, 0(t0)
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# Access fault on top level PTE
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li t0, 0x1000000000
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lw t1, 0(t0)
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# Bad PBMT on top level PTE
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li t0, 0x1800000000
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lw t1, 0(t0)
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# Access fault on megapage
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li t0, 0x81400000
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lw t1, 0(t0)
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# Access fault walking page tables at megapage level
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li t0, 0xC0000000
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lw t1, 0(t0)
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# AMO operation on page table entry that causes page fault due to malformed PBMT
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li t0, 0x81200000
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jalr t0 # Attempt to fetch instruction from address causing faulty page walk
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lw t1, 0(t0)
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sfence.vma
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amoadd.w t0, t0, 0(t0)
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# point top-level page table to an illegal address and verify it faults
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li t0, 0x9000000000070000 # trap handler at non-existing memory location
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csrw satp, t0 # should cause trap
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sfence.vma
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nop
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# change back to default trap handler after checking everything that might cause an instruction page fault
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jal changetodefaulthandler
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# uncachable AMO access
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li t0, 0x80401000 # PBMT sets as uncachable
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amoadd.w t0, t0, 0(t0)
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# exercise CBOM instructions with various permissions
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li t0, 0x80800000
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cbo.zero (t0)
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cbo.clean (t0)
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li t0, 0x80801000
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cbo.zero (t0)
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cbo.clean (t0)
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li t0, 0x80802000
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cbo.zero (t0)
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cbo.clean (t0)
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li t0, 0x80803000
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cbo.zero (t0)
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cbo.clean (t0)
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li t0, 0x80804000
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cbo.zero (t0)
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cbo.clean (t0)
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# set mstatus.MXR
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li a0, 3
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ecall
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li t0, 1
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slli t0, t0, 19
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csrs mstatus, t0 # mstatus.mxr = 1
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li a0, 1
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ecall
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# exercise CBOM again now that MXR is set
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li t0, 0x80800000
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cbo.zero (t0)
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cbo.clean (t0)
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li t0, 0x80801000
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cbo.zero (t0)
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cbo.clean (t0)
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li t0, 0x80802000
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cbo.zero (t0)
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cbo.clean (t0)
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li t0, 0x80803000
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cbo.zero (t0)
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cbo.clean (t0)
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li t0, 0x80804000
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cbo.zero (t0)
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cbo.clean (t0)
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# clear mstatus.MXR
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li a0, 3
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ecall
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li t0, 1
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slli t0, t0, 19
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csrc mstatus, t0 # mstatus.mxr = 1
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li a0, 1
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ecall
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# wrap up
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li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
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ecall
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j done
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backandforth:
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ret
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changetoipfhandler:
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li a0, 3
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ecall # switch to machine mode
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la a0, ipf_handler
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csrw mtvec, a0 # point to new handler
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li a0, 1
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ecall # switch back to supervisor mode
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ret
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changetodefaulthandler:
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li a0, 3
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ecall # switch to machine mode
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la a0, trap_handler
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csrw mtvec, a0 # point to new handler
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li a0, 1
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ecall # switch back to supervisor mode
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ret
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instructionpagefaulthandler:
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csrw mepc, ra # go back to calling function
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mret
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.align 4 # trap handlers must be aligned to multiple of 16
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ipf_handler:
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# Load trap handler stack pointer tp
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csrrw tp, mscratch, tp # swap MSCRATCH and tp
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sd t0, 0(tp) # Save t0 and t1 on the stack
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sd t1, -8(tp)
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li t5, 0x9000000000080010
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csrw satp, t5 # make sure we are pointing to the root page table
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csrr t0, mcause # Check the cause
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li t1, 8 # is it an ecall trap?
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andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
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beq t0, t1, ecall # yes, take ecall
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csrr t0, mcause
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li t1, 12 # is it an instruction page fault
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beq t0, t1, ipf # yes, return to calling function
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j trap_return
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ipf:
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csrw mepc, ra # return to calling function
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ld t1, -8(tp) # restore t1 and t0
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ld t0, 0(tp)
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csrrw tp, mscratch, tp # restore tp
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mret # return from trap
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.align 4 # trap handlers must be aligned to multiple of 16
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fixsatptraphandler:
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li t5, 0x9000000000080010 # fix satp entry to normal page table root
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csrw satp, t5
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mret
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.data
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.align 16
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# root Page table situated at 0x80010000
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pagetable:
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.8byte 0x200044C1 # VA 0x00000000-0x7F_FFFFFFFF: PTE at 0x80011000 C1 dirty, accessed, valid
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.8byte 0x00000000000010CF # misaligned terapage at 0x80_00000000
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.8byte 0x00000000000000CF # access fault terapage at 0x100_00000000
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.8byte 0x40000000200044C1 # Bad PBMT at VA 0x180_0000000
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# next page table at 0x80011000
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.align 12
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.8byte 0x00000000000010CF # misaligned gigapage at 0x00000000
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.8byte 0x00000000200058C1 # PTE for pages at 0x40000000 pointing to 0x80150000
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.8byte 0x00000000200048C1 # gigapage at 0x80000000 pointing to 0x80120000
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.8byte 0x00000000000000C1 # gigapage at VA 0xC0000000 causes access fault
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.8byte 0x0
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.8byte 0x0
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.8byte 0x0
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.8byte 0x0
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SpecialPage:
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.8byte 0x00000000200000CF # 0x2_0000_0000 1GiB page1
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# Next page table at 0x80012000 for gigapage at 0x80000000
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.align 12
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.8byte 0x0000000020004CC1 # for VA starting at 80000000 (pointer to NAPOT 64 KiB pages Page table at 80013000)
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.8byte 0x0000000020014CCF # for VA starting at 80200000 (misaligned megapage)
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.8byte 0x00000000200050C1 # for VA starting at 80400000 (bad PBMT pages page table at 0x80014000)
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.8byte 0x4000000020004CC1 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
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.8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz . page table at 0x80015000)
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.8byte 0x0000000020004CC1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000. page table at 0x80013000)
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.8byte 0x0F00000020004CCF # for VA starting at 80C00000 (bad reserved field in bits 60:54)
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.8byte 0x000000002000000F # for VA starting at 80E00000 (megapage not dirty or accessed)
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.8byte 0x0000000000004CC1 # for VA starting at 81000000 (nonleaf pointing to unimplemented memory causes access fault)
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.8byte 0x4000000020004CC1 # for VA starting at 81200000 (nonleaf with PBMT nonzero causes page fault)
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.8byte 0x00000000000000CF # for VA starting at 81400000 (megapage with access fault)
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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# Leaf page table at 0x80013000 with 64 KiB NAPOT pages
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.align 12
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#80000000
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0xA0000000200020CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x80000000200060CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000A0CF
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.8byte 0x800000002000E0CF
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.8byte 0x800000002000E0CF
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.8byte 0x800000002000E0CF
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.8byte 0x800000002000E0CF
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.8byte 0x800000002000E0CF
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.8byte 0x800000002000E0CF
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# Leaf page table at 0x80014000 with PBMT pages
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.align 12
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#80400000
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.8byte 0x60000000200020CF # reserved entry VA 80400000
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.8byte 0x40000000201000CF # non-cache non-idempotent VA 80401000
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# Leaf page table at 0x80015000 with various permissions for testing CBOM and CBOZ
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.align 12
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#80800000
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.8byte 0x00000000200000CF # valid rwx for VA 80800000
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.8byte 0x00000000200000CB # valid r x for VA 80801000
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.8byte 0x00000000200000C3 # valid r for VA 80802000
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.8byte 0x00000000200000C9 # valid x for VA 80803000
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.8byte 0x00000000200000CD # valid wx for VA 80804000 (illegal combination, but used to test tlbcontrol)
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.8byte 0x00000000200000CF # valid rwx for VA 80805000 for covering ITLB translate
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.8byte 0x20000000200000CF # PBMT=1 for VA 80806000 for covering ITLB BadPBMT
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.8byte 0x000000002000000F # valid rwx for VA 80807000 for covering UpdateDA
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