mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
5 lines
116 B
Systemverilog
5 lines
116 B
Systemverilog
module BUFGMUX(input logic I1, input logic I0, input logic S, output logic O);
|
|
|
|
assign O = S ? I1 : I0;
|
|
endmodule
|