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cvw/addins
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Jordan Carlin 96af5d1618
Merge pull request #1225 from openhwgroup/dependabot/submodules/addins/vivado-boards-d1898bd 
Bump addins/vivado-boards from `8ed4f99` to `d1898bd`
2025-01-07 10:17:42 -08:00
..
berkeley-softfloat-3@3b70b5d814 Add softfloat as submodule 2024-09-15 00:20:39 -07:00
berkeley-testfloat-3@03c13d21db Switch to using testfloat submodule 2024-09-15 00:37:04 -07:00
branch-predictor-simulator@3e424e902f Swap in branch predictor simulator handling compressed instruction offsets 2023-11-21 16:42:41 -08:00
coremark@f3e8f2e094 added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug) 2022-06-13 23:23:57 +00:00
cvw-arch-verif@cdc4005363 Bump addins/cvw-arch-verif from acf99b1 to cdc4005 2025-01-06 14:07:14 +00:00
embench-iot@54fd9a0f10 repo cleanup and start to add CMO tests 2023-11-20 23:41:36 -08:00
riscv-arch-test@832ab11c09 Update riscv-arch-test again 2024-12-31 02:23:05 -08:00
riscv-dv@f0c570d112 /cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch 2024-04-26 15:55:39 -07:00
verilog-ethernet@c180b22ed5 Revert "Bump addins/verilog-ethernet from c180b22 to 6f5ea41" 2024-11-26 08:15:36 -08:00
vivado-boards@d1898bd01f Bump addins/vivado-boards from 8ed4f99 to d1898bd 2025-01-06 14:07:12 +00:00
README.md Added some documenation about sparse-checkout for verilog-ethernet submodule. 2024-07-19 13:11:48 -05:00
sparse-checkout Cleanup in prep to merge the rvvi branch into main. 2024-07-19 15:48:20 -05:00

README.md

verilog-ethernet contains many ethernet devices. Wally's synthesizable RVVI interface only requires a small subset of these files. To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info This will make the working directory only contain the necessary files.