bbracker bb2e3b1e02 remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux		2021-07-19 16:22:05 -04:00
..
slack-notifier	added slack notifier for long sims	2021-06-22 08:31:41 -04:00
wave-dos	make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset	2021-07-19 15:13:03 -04:00
regression-wally.py	remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux	2021-07-19 16:22:05 -04:00
run_sim.sh
sim-buildroot
sim-buildroot-batch
sim-busybear
sim-busybear-batch
sim-wally
sim-wally-batch
sim-wally-batch-muldiv
sim-wally-batch-rv32ic
sim-wally-batch-rv32icfd	Fixed lint warning	2021-07-14 21:24:48 -04:00
sim-wally-batch-rv64icfd
sim-wally-muldiv
sim-wally-rv32ic
sim-wally-rv32icfd	Fixed lint warning	2021-07-14 21:24:48 -04:00
sim-wally-rv64icfd	Double-precision FMA instructions	2021-06-04 14:00:11 -04:00
udiv.c
wally-buildroot-batch.do	whoops meant to remove notifications from busybear, not buildroot	2021-06-24 01:54:46 -04:00
wally-buildroot.do	whoops meant to remove notifications from busybear, not buildroot	2021-06-24 01:54:46 -04:00
wally-busybear-batch.do	hptw: minor cleanup	2021-07-17 13:40:12 -04:00
wally-busybear.do	stop busybear from hanging	2021-07-02 17:22:09 -05:00
wally-coremark_bare.do
wally-pipelined-batch-muldiv.do
wally-pipelined-batch-rv32icfd.do	Fixed lint warning	2021-07-14 21:24:48 -04:00
wally-pipelined-batch-rv64icfd.do	fdivsqrt inegrated, but not completley working	2021-07-18 14:03:37 -04:00
wally-pipelined-batch.do	hptw: minor cleanup	2021-07-17 13:40:12 -04:00
wally-pipelined-muldiv.do
wally-pipelined-ross.do	Works until pma checker breaks the simulation by reading HADDR rather than data physical address.	2021-06-24 14:42:59 -05:00
wally-pipelined-rv32icfd.do	Fixed lint warning	2021-07-14 21:24:48 -04:00
wally-pipelined-rv64icfd.do	fdivsqrt inegrated, but not completley working	2021-07-18 14:03:37 -04:00
wally-pipelined.do
wally-privileged.do
wave-all.do	Fixed busybear by restoring InstrValidW needed by testbench	2021-07-13 14:17:36 -04:00
wave.do	Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW.	2021-07-19 12:32:16 -05:00