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24 lines
850 B
Systemverilog
24 lines
850 B
Systemverilog
import cvw::*;
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`include "config.vh"
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`include "parameter-defs.vh"
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module wallypipelinedcorewrapper (
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input logic clk, reset,
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// Privileged
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input logic MTimerInt, MExtInt, SExtInt, MSwInt,
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input logic [63:0] MTIME_CLINT,
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// Bus Interface
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input logic [P.AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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output logic HCLK, HRESETn,
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output logic [P.PA_BITS-1:0] HADDR,
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output logic [P.AHBW-1:0] HWDATA,
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output logic [P.XLEN/8-1:0] HWSTRB,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK
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);
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wallypipelinedcore #(P) dut(.*);
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endmodule |