mirror of
https://github.com/openhwgroup/cvw
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127 lines
5.6 KiB
Systemverilog
127 lines
5.6 KiB
Systemverilog
//////////////////////////////////////////
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// wally-shared.vh
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//
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// Written: david_harris@hmc.edu 7 June 2021
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//
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// Purpose: Shared and default configuration values common to all designs
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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// include shared constants
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`include "wally-constants.vh"
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// macros to define supported modes
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// NOTE: No hardware support fo Q yet
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`define A_SUPPORTED ((`MISA >> 0) % 2 == 1)
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`define C_SUPPORTED ((`MISA >> 2) % 2 == 1)
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`define D_SUPPORTED ((`MISA >> 3) % 2 == 1)
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`define E_SUPPORTED ((`MISA >> 4) % 2 == 1)
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`define F_SUPPORTED ((`MISA >> 5) % 2 == 1)
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`define I_SUPPORTED ((`MISA >> 8) % 2 == 1)
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`define M_SUPPORTED ((`MISA >> 12) % 2 == 1)
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`define Q_SUPPORTED ((`MISA >> 16) % 2 == 1)
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`define S_SUPPORTED ((`MISA >> 18) % 2 == 1)
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`define U_SUPPORTED ((`MISA >> 20) % 2 == 1)
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// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
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//`define N_SUPPORTED ((MISA >> 13) % 2 == 1)
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`define N_SUPPORTED 0
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// logarithm of XLEN, used for number of index bits to select
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`define LOG_XLEN (`XLEN == 32 ? 5 : 6)
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// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
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`define PMPCFG_ENTRIES (`PMP_ENTRIES/8)
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// Floating point constants for Quad, Double, Single, and Half precisions
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`define Q_LEN 32'd128
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`define Q_NE 32'd15
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`define Q_NF 32'd112
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`define Q_BIAS 32'd16383
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`define Q_FMT 2'd3
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`define D_LEN 32'd64
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`define D_NE 32'd11
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`define D_NF 32'd52
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`define D_BIAS 32'd1023
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`define D_FMT 2'd1
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`define S_LEN 32'd32
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`define S_NE 32'd8
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`define S_NF 32'd23
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`define S_BIAS 32'd127
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`define S_FMT 2'd0
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`define H_LEN 32'd16
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`define H_NE 32'd5
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`define H_NF 32'd10
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`define H_BIAS 32'd15
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`define H_FMT 2'd2
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// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
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`define FLEN (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `F_SUPPORTED ? `S_LEN : `H_LEN)
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`define NE (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `F_SUPPORTED ? `S_NE : `H_NE)
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`define NF (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `F_SUPPORTED ? `S_NF : `H_NF)
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`define FMT (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : `F_SUPPORTED ? 2'd0 : 2'd2)
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`define BIAS (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `F_SUPPORTED ? `S_BIAS : `H_BIAS)
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// Floating point constants needed for FPU paramerterization
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`define FPSIZES ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED))
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`define FMTBITS ((32)'(`FPSIZES>=3)+1)
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`define LEN1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN)
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`define NE1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE)
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`define NF1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF)
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`define FMT1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2)
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`define BIAS1 ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS)
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`define LEN2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN)
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`define NE2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE)
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`define NF2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF)
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`define FMT2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2)
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`define BIAS2 ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS)
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// largest length in IEU/FPU
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`define CVTLEN ((`NF<`XLEN) ? (`XLEN) : (`NF))
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`define LLEN ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN))
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`define LOGCVTLEN $unsigned($clog2(`CVTLEN+1))
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`define NORMSHIFTSZ ((`QLEN+`NF+3) > (3*`NF+8) ? (`QLEN+`NF+1) : (3*`NF+9))
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`define CORRSHIFTSZ ((`DIVRESLEN+`NF) > (3*`NF+8) ? (`DIVRESLEN+`NF) : (3*`NF+6))
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// division constants
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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`define DIVLEN ((`NF < `XLEN) ? (`XLEN) : (`NF + 3))
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`define DIVN (`NF < `XLEN ? `XLEN : `NF+1) // length of input
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`define EXTRAFRACBITS ((`NF<(`XLEN)) ? (`XLEN - `NF) : 3)
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`define EXTRAINTBITS ((`NF<(`XLEN)) ? 0 : (`NF - `XLEN + 3))
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`define DIVRESLEN ((`NF>`XLEN) ? `NF+4 : `XLEN)
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`define LOGR ((`RADIX==2) ? 32'h1 : 32'h2)
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// FPDUR = ceil(DIVRESLEN/(LOGR*DIVCOPIES))
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// one interation is required for the integer bit for minimally redundent radix-4
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`define FPDUR ((`DIVLEN+(`LOGR*`DIVCOPIES)-1)/(`LOGR*`DIVCOPIES)+(`RADIX/4))
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`define DURLEN ($clog2(`FPDUR+1))
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`define QLEN (`FPDUR*`LOGR*`DIVCOPIES)
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`define DIVb (`FPDUR*`LOGR*`DIVCOPIES)-1
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`define USE_SRAM 0
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// Disable spurious Verilator warnings
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/* verilator lint_off STMTDLY */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off PINCONNECTEMPTY */
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