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https://github.com/openhwgroup/cvw
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245 lines
12 KiB
Systemverilog
245 lines
12 KiB
Systemverilog
///////////////////////////////////////////
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// pagetablewalker.sv
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//
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// Written: tfleming@hmc.edu 2 March 2021
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// Modified: kmacsaigoren@hmc.edu 1 June 2021
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// implemented SV48 on top of SV39. This included, adding a level of the FSM for the extra page number segment
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// adding support for terapage encoding, and for setting the TranslationPAdr using the new level,
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// adding the internal SvMode signal
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//
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// Purpose: Page Table Walker
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// Part of the Memory Management Unit (MMU)
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module pagetablewalker
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(
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// Control signals
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input logic clk, reset,
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input logic [`XLEN-1:0] SATP_REGW,
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// Signals from TLBs (addresses to translate)
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input logic [`XLEN-1:0] PCF, MemAdrM,
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input logic ITLBMissF, DTLBMissM,
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input logic [1:0] MemRWM,
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// Outputs to the TLBs (PTEs to write)
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output logic [`XLEN-1:0] PTE, //PageTableEntryM,
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output logic [1:0] PageType,
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output logic ITLBWriteF, DTLBWriteM,
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output logic SelPTW,
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// *** modify to send to LSU // *** KMG: These are inputs/results from the ahblite whose addresses should have already been checked, so I don't think they need to be sent through the LSU
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input logic [`XLEN-1:0] HPTWReadPTE,
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input logic HPTWStall,
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// *** modify to send to LSU
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output logic [`XLEN-1:0] HPTWPAdrE, // this probalby should be `PA_BITS wide
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output logic [`XLEN-1:0] HPTWPAdrM, // this probalby should be `PA_BITS wide
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output logic HPTWRead,
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// Faults
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output logic WalkerInstrPageFaultF,
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output logic WalkerLoadPageFaultM,
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output logic WalkerStorePageFaultM
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);
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generate
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if (`MEM_VIRTMEM) begin
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// Internal signals
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logic DTLBWalk; // register TLBs translation miss requests
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logic [`PPN_BITS-1:0] BasePageTablePPN;
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logic [`XLEN-1:0] TranslationVAdr;
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logic [`PA_BITS-1:0] TranslationPAdr;
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logic [`PPN_BITS-1:0] CurrentPPN;
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logic MemWrite;
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logic Executable, Writable, Readable, Valid;
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logic MegapageMisaligned, GigapageMisaligned, TerapageMisaligned;
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logic ValidPTE, LeafPTE, ValidLeafPTE, ValidNonLeafPTE;
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logic StartWalk;
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logic EndWalk;
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logic PRegEn;
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logic [1:0] NextPageType;
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logic [`SVMODE_BITS-1:0] SvMode;
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typedef enum {LEVEL0_SET_ADR, LEVEL0_READ, LEVEL0,
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LEVEL1_SET_ADR, LEVEL1_READ, LEVEL1,
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LEVEL2_SET_ADR, LEVEL2_READ, LEVEL2,
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LEVEL3_SET_ADR, LEVEL3_READ, LEVEL3,
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LEAF, IDLE, FAULT} statetype;
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statetype WalkerState, NextWalkerState, InitialWalkerState;
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// Extract bits from CSRs and inputs
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assign SvMode = SATP_REGW[`XLEN-1:`XLEN-`SVMODE_BITS];
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assign BasePageTablePPN = SATP_REGW[`PPN_BITS-1:0];
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assign MemWrite = MemRWM[0];
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// Determine which address to translate
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assign TranslationVAdr = DTLBWalk ? MemAdrM : PCF;
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flop #(`XLEN) HPTWPAdrMReg(clk, HPTWPAdrE, HPTWPAdrM);
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flopenrc #(1) TLBMissMReg(clk, reset, EndWalk, StartWalk | EndWalk, DTLBMissM, DTLBWalk);
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset, 1'b1, NextWalkerState, IDLE, WalkerState);
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flopenr #(`XLEN) PTEReg(clk, reset, PRegEn, HPTWReadPTE, PTE); // Capture page table entry from data cache
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assign CurrentPPN = PTE[`PPN_BITS+9:10];
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// Assign PTE descriptors common across all XLEN values
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// For non-leaf PTEs, D, A, U bits are reserved and ignored. They do not cause faults while walking the page table
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assign {Executable, Writable, Readable, Valid} = PTE[3:0];
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assign LeafPTE = Executable | Writable | Readable;
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assign ValidPTE = Valid && ~(Writable && ~Readable);
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assign ValidLeafPTE = ValidPTE & LeafPTE;
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assign ValidNonLeafPTE = ValidPTE & ~LeafPTE;
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// Enable and select signals based on states
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assign StartWalk = (WalkerState == IDLE) & (DTLBMissM | ITLBMissF);
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assign EndWalk = (WalkerState == LEAF) || (WalkerState == FAULT);
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assign PRegEn = (NextWalkerState == LEVEL3) | (NextWalkerState == LEVEL2) | (NextWalkerState == LEVEL1) | (NextWalkerState == LEVEL0);
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assign HPTWRead = (WalkerState == LEVEL3_READ) | (WalkerState == LEVEL2_READ) | (WalkerState == LEVEL1_READ) | (WalkerState == LEVEL0_READ);
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assign SelPTW = (WalkerState != IDLE) & (WalkerState != FAULT);
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assign DTLBWriteM = (WalkerState == LEAF) & DTLBWalk;
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assign ITLBWriteF = (WalkerState == LEAF) & ~DTLBWalk;
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// Raise faults. DTLBMiss
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assign WalkerInstrPageFaultF = (WalkerState == FAULT) & ~DTLBWalk;
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assign WalkerLoadPageFaultM = (WalkerState == FAULT) & DTLBWalk & ~MemWrite;
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assign WalkerStorePageFaultM = (WalkerState == FAULT) & DTLBWalk & MemWrite;
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// FSM to track PageType based on the levels of the page table traversed
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flopr #(2) PageTypeReg(clk, reset, NextPageType, PageType);
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always_comb
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case (WalkerState)
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LEVEL3: NextPageType = 2'b11; // terapage
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LEVEL2: NextPageType = 2'b10; // gigapage
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LEVEL1: NextPageType = 2'b01; // megapage
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LEVEL0: NextPageType = 2'b00; // kilopage
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default: NextPageType = PageType;
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endcase
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// TranslationPAdr mux
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if (`XLEN==32) begin
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logic [9:0] VPN1, VPN0;
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assign VPN1 = TranslationVAdr[31:22];
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assign VPN0 = TranslationVAdr[21:12];
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always_comb
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case (WalkerState)
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LEVEL1_SET_ADR: TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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LEVEL1_READ: TranslationPAdr = {BasePageTablePPN, VPN1, 2'b00};
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LEVEL1: if (NextWalkerState == LEAF) TranslationPAdr = {2'b00, TranslationVAdr[31:0]}; // ***check this and similar in LEVEL0 and LEAF
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else TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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LEVEL0_SET_ADR: TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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LEVEL0_READ: TranslationPAdr = {CurrentPPN, VPN0, 2'b00};
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LEVEL0: TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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LEAF: TranslationPAdr = {2'b00, TranslationVAdr[31:0]};
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default: TranslationPAdr = 0; // cause seg fault if this is improperly used
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endcase
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end else begin
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logic [8:0] VPN3, VPN2, VPN1, VPN0;
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assign VPN3 = TranslationVAdr[47:39];
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assign VPN2 = TranslationVAdr[38:30];
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assign VPN1 = TranslationVAdr[29:21];
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assign VPN0 = TranslationVAdr[20:12];
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always_comb
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case (WalkerState)
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LEVEL3_SET_ADR: TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
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LEVEL3_READ: TranslationPAdr = {BasePageTablePPN, VPN3, 3'b000};
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LEVEL3: if (NextWalkerState == LEAF) TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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else TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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LEVEL2_SET_ADR: TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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LEVEL2_READ: TranslationPAdr = {(SvMode == `SV48) ? CurrentPPN : BasePageTablePPN, VPN2, 3'b000};
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LEVEL2: if (NextWalkerState == LEAF) TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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else TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
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LEVEL1_SET_ADR: TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
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LEVEL1_READ: TranslationPAdr = {CurrentPPN, VPN1, 3'b000};
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LEVEL1: if (NextWalkerState == LEAF) TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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else TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
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LEVEL0_SET_ADR: TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
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LEVEL0_READ: TranslationPAdr = {CurrentPPN, VPN0, 3'b000};
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LEVEL0: TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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LEAF: TranslationPAdr = TranslationVAdr[`PA_BITS-1:0];
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default: TranslationPAdr = 0; // cause seg fault if this is improperly used
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endcase
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end
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if (`XLEN == 32) begin
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assign InitialWalkerState = LEVEL1_SET_ADR;
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assign TerapageMisaligned = 0; // not applicable
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assign GigapageMisaligned = 0; // not applicable
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assign MegapageMisaligned = |(CurrentPPN[9:0]); // must have zero PPN0
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assign HPTWPAdrE = TranslationPAdr[31:0]; // ***not right?
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end else begin
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assign InitialWalkerState = (SvMode == `SV48) ? LEVEL3_SET_ADR : LEVEL2_SET_ADR;
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assign TerapageMisaligned = |(CurrentPPN[26:0]); // must have zero PPN2, PPN1, PPN0
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assign GigapageMisaligned = |(CurrentPPN[17:0]); // must have zero PPN1 and PPN0
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assign MegapageMisaligned = |(CurrentPPN[8:0]); // must have zero PPN0
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assign HPTWPAdrE = {{(`XLEN-`PA_BITS){1'b0}}, TranslationPAdr[`PA_BITS-1:0]};
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end
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// Page Table Walker FSM
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// ***Is there a w ay to reduce the number of cycles needed to do the walk?
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always_comb
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case (WalkerState)
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IDLE: if (StartWalk) NextWalkerState = InitialWalkerState;
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else NextWalkerState = IDLE;
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LEVEL3_SET_ADR: NextWalkerState = LEVEL3_READ;
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LEVEL3_READ: if (HPTWStall) NextWalkerState = LEVEL3_READ;
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else NextWalkerState = LEVEL3;
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LEVEL3: if (ValidLeafPTE && ~TerapageMisaligned) NextWalkerState = LEAF;
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else if (ValidNonLeafPTE) NextWalkerState = LEVEL2_SET_ADR;
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else NextWalkerState = FAULT;
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LEVEL2_SET_ADR: NextWalkerState = LEVEL2_READ;
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LEVEL2_READ: if (HPTWStall) NextWalkerState = LEVEL2_READ;
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else NextWalkerState = LEVEL2;
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LEVEL2: if (ValidLeafPTE && ~GigapageMisaligned) NextWalkerState = LEAF;
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else if (ValidNonLeafPTE) NextWalkerState = LEVEL1_SET_ADR;
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else NextWalkerState = FAULT;
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LEVEL1_SET_ADR: NextWalkerState = LEVEL1_READ;
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LEVEL1_READ: if (HPTWStall) NextWalkerState = LEVEL1_READ;
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else NextWalkerState = LEVEL1;
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LEVEL1: if (ValidLeafPTE && ~MegapageMisaligned) NextWalkerState = LEAF;
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else if (ValidNonLeafPTE) NextWalkerState = LEVEL0_SET_ADR;
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else NextWalkerState = FAULT;
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LEVEL0_SET_ADR: NextWalkerState = LEVEL0_READ;
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LEVEL0_READ: if (HPTWStall) NextWalkerState = LEVEL0_READ;
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else NextWalkerState = LEVEL0;
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LEVEL0: if (ValidLeafPTE) NextWalkerState = LEAF;
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else NextWalkerState = FAULT;
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LEAF: NextWalkerState = IDLE;
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FAULT: NextWalkerState = IDLE;
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default: begin
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$error("Default state in HPTW should be unreachable");
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NextWalkerState = IDLE; // should never be reached
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end
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endcase
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end else begin
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assign HPTWPAdrE = 0;
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assign HPTWRead = 0;
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assign WalkerInstrPageFaultF = 0;
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assign WalkerLoadPageFaultM = 0;
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assign WalkerStorePageFaultM = 0;
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assign SelPTW = 0;
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end
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endgenerate
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endmodule
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