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https://github.com/openhwgroup/cvw
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66 lines
1.1 KiB
Systemverilog
66 lines
1.1 KiB
Systemverilog
`include "../../config/rv64icfd/wally-config.vh"
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module fputop (
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input logic [2:0] FrmW,
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input logic reset,
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input logic clear,
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input logic clk,
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input logic [31:0] InstrD,
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input logic [`XLEN-1:0] SrcAE,
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input logic [`XLEN-1:0] SrcAW,
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output logic [31:0] FSROutW,
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output logic DivSqrtDoneE,
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output logic FInvalInstrD,
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output logic [`XLEN-1:0] FPUResultW);
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/*fctrl ();
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//regfile instantiation and decode stage
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//write signal mux
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//address signal mux
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//parallel floating-point registers are
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//used for modularity and future performance
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//comparisons between operation sets
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freg1adr ();
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freg2adr ();
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freg2adr ();
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freg2adr ();
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freg3adr ();
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//can easily be merged into privledged core
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//if necessary
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fcsr ();
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//E pipe and execution stage
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fpdivsqrt ();
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fma1 ();
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fpaddcvt1 ();
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fpcmp1 ();
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fpsign ();
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//M pipe and memory stage
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fma2 ();
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fpaddcvt2 ();
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fpcmp2 ();
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//W pipe and writeback stage
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//flag signal mux
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*/
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endmodule
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