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Configurable RISC-V Processor
1,578 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
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Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
e1319a2fbe
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Ross Thompson e1319a2fbe Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts.
2021-08-06 16:06:50 -05:00
riscv-coremark Updated location to find compiler for coremark 2021-07-16 19:13:18 -04:00
testsBP
wally-pipelined Partial conversion of the linux trace checking to read in the file in the Memory Stage so it is possible to overwrite registers, memory, and interrupts. 2021-08-06 16:06:50 -05:00
.gitattributes
.gitignore separated buildroot debugging from buildroot logging 2021-07-17 14:52:34 -04:00
.gitmodules Flow updated for 90nm 2021-07-01 13:32:42 -05:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor