mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
79 lines
1.9 KiB
Plaintext
Executable File
79 lines
1.9 KiB
Plaintext
Executable File
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# Search Paths
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set CURRENT_DIR [exec pwd]
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set search_path [list "./" ]
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set s8lib ../addins/sky130_osu_sc_t12/12T_ms/lib
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lappend search_path $s8lib
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# Synthetic libraries
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set synthetic_library [list dw_foundation.sldb]
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# Set OKSTATE standard cell libraries
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set target_library [list]
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lappend target_library sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db
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# Set Link Library
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set link_library "$target_library $synthetic_library"
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# Set up DesignWare cache read and write directories to speed up compile.
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set cache_write ~
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set cache_read $cache_write
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# Tell DC where to look for files
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lappend search_path ./scripts
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lappend search_path ./hdl
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lappend search_path ./mapped
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# Set up User Information
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set company "Oklahoma State University"
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set user "James E. Stine"
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# Alias
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alias ra report_area
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alias rt report_timing
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alias rc {report_constraint -all_violators}
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alias sf set_flatten
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alias ss set_structure
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alias rco report_compile_options
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alias cs compile -scan
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alias csi compile -scan -incr -map high
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alias h history
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history keep 100
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alias all_gone {remove_design -designs}
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alias page_on {set sh_enable_page_mode true}
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alias page_off {set sh_enable_page_mode false}
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# specify directory for intermediate files from analyze
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define_design_lib DEFAULT -path ./analyzed
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# suppress Driving cell warning
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suppress_message {UID-401}
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########### Source Useful Tcl Procedures ###########
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foreach _file [glob -nocomplain ./tcl_procs/*.tcl] {
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source $_file
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}
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############# Enable line editing in 2004.12 ###########
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set sh_enable_line_editing true
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############# Setup the view utility ###########
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proc view {args} {
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redirect tmpfile1212 {uplevel $args}
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# Without redirect, exec echos the PID of the new process to the screen
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redirect /dev/null {exec ./tcl_procs/view.tk tmpfile1212 "$args" &}
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}
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alias vrt {view report_timing -nosplit}
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alias vrtm {view report_timing -nosplit -delay min}
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alias vman {view man}
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