mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
496 lines
52 KiB
Plaintext
496 lines
52 KiB
Plaintext
onerror {resume}
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quietly virtual function -install /testbench/dut/core/ifu -env /testbench/dut/core/ifu { &{/testbench/dut/core/ifu/BPPredWrongM, /testbench/dut/core/ifu/InvalidateICacheM }} temp
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quietly WaveActivateNextPane {} 0
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -noupdate /testbench/reset_ext
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add wave -noupdate -radix unsigned /testbench/InstrCountW
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add wave -noupdate /testbench/dut/core/SATP_REGW
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add wave -noupdate /testbench/dut/core/IllegalFPUInstrD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/BPPredWrongE
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/CSRWritePendingDEM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/RetM
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add wave -noupdate -group HDU -expand -group hazards -color Pink /testbench/dut/core/hzu/TrapM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LoadStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/StoreStallD
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/LSUStallM
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add wave -noupdate -group HDU -expand -group hazards /testbench/dut/core/hzu/DivBusyE
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/ExceptionM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/IllegalInstrFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadAccessFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InstrPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/BreakpointFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/EcallFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadMisalignedFaultM
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add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoAccessFaultM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushD
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushE
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushM
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add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/core/FlushW
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallF
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallD
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
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add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
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add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/FinalInstrRawF
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
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add wave -noupdate -group {Decode Stage} /testbench/InstrDName
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/InstrValidD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/c/RegWriteD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
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add wave -noupdate -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/PCE
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add wave -noupdate -group {Execution Stage} /testbench/ExpectedPCE
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add wave -noupdate -group {Execution Stage} /testbench/MepcExpected
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ifu/InstrE
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add wave -noupdate -group {Execution Stage} /testbench/InstrEName
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add wave -noupdate -group {Execution Stage} /testbench/dut/core/ieu/c/InstrValidE
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add wave -noupdate -group {Execution Stage} /testbench/textE
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add wave -noupdate -group {Execution Stage} -color {Cornflower Blue} /testbench/FunctionName/FunctionName
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add wave -noupdate -expand -group {Memory Stage} /testbench/checkInstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/PCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/ExpectedPCM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/InstrM
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add wave -noupdate -expand -group {Memory Stage} /testbench/InstrMName
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add wave -noupdate -expand -group {Memory Stage} /testbench/textM
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add wave -noupdate -expand -group {Memory Stage} /testbench/dut/core/lsu/IEUAdrM
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add wave -noupdate -group {WriteBack stage} /testbench/checkInstrW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrValidW
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add wave -noupdate -group {WriteBack stage} /testbench/PCW
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add wave -noupdate -group {WriteBack stage} /testbench/ExpectedPCW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrW
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add wave -noupdate -group {WriteBack stage} /testbench/InstrWName
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add wave -noupdate -group {WriteBack stage} /testbench/textW
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add wave -noupdate -group Bpred -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHR
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
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add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
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add wave -noupdate -group Bpred -group {branch update selection inputs} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPInstrClassE[0]}
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPPredDirWrongE
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add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightNonCFI
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongCFI
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
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add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
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add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr0
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr1
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateEN
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRLookup
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCNextF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/RA1
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add wave -noupdate -group Bpred -expand -group prediction -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
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add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
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add wave -noupdate -group Bpred -expand -group prediction -expand -group ex -radix binary /testbench/dut/core/ifu/bpred/bpred/BPPredE
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add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
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add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/BPPredDirWrongE
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
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add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
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add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
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add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCE
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add wave -noupdate -group Bpred -expand -group update -expand -group direction /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHT/WA1
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
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add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
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add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group PCS /testbench/dut/core/PCF
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add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
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add wave -noupdate -group PCS /testbench/dut/core/PCE
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add wave -noupdate -group PCS /testbench/dut/core/PCM
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add wave -noupdate -group PCS /testbench/PCW
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredPCF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext0F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/SelBPPredF
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
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add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PrivilegedChangePCM
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add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a1
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a2
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/a3
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/we3
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add wave -noupdate -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ReadDataW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/CSRReadValW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultSrcW
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add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/core/ieu/dp/ResultW
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add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/A
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add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/B
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add wave -noupdate -group alu /testbench/dut/core/ieu/dp/alu/ALUControl
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add wave -noupdate -group alu -divider internals
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1D
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2D
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs1E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/Rs2E
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/MemReadE
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteM
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add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RegWriteW
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardAE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/ForwardBE
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add wave -noupdate -group Forward -color Thistle /testbench/dut/core/ieu/fw/LoadStallD
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/WriteDataE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
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add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
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add wave -noupdate -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
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add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/icache/ReadDataWord
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add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
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add wave -noupdate -group icache /testbench/dut/core/ifu/bus/icache/icache/RAdr
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/CacheHit
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/CacheStall
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add wave -noupdate -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/ReadDataLineSets
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add wave -noupdate -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheMemWriteData
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add wave -noupdate -group icache /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
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add wave -noupdate -group AHB -color Gold /testbench/dut/core/ebu/BusState
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add wave -noupdate -group AHB /testbench/dut/core/ebu/NextBusState
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add wave -noupdate -group AHB -expand -group {input requests} /testbench/dut/core/ebu/AtomicMaskedM
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add wave -noupdate -group AHB /testbench/dut/core/ebu/HCLK
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add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESETn
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add wave -noupdate -group AHB /testbench/dut/core/ebu/HRDATA
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add wave -noupdate -group AHB /testbench/dut/core/ebu/HREADY
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add wave -noupdate -group AHB /testbench/dut/core/ebu/HRESP
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add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDR
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add wave -noupdate -group AHB /testbench/dut/core/ebu/HWDATA
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add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITE
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add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZE
|
|
add wave -noupdate -group AHB /testbench/dut/core/ebu/HBURST
|
|
add wave -noupdate -group AHB /testbench/dut/core/ebu/HPROT
|
|
add wave -noupdate -group AHB /testbench/dut/core/ebu/HTRANS
|
|
add wave -noupdate -group AHB /testbench/dut/core/ebu/HMASTLOCK
|
|
add wave -noupdate -group AHB /testbench/dut/core/ebu/HADDRD
|
|
add wave -noupdate -group AHB /testbench/dut/core/ebu/HSIZED
|
|
add wave -noupdate -group AHB /testbench/dut/core/ebu/HWRITED
|
|
add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/funct
|
|
add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/result
|
|
add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/srca
|
|
add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/srcb
|
|
add wave -noupdate -group AMO_ALU /testbench/dut/core/lsu/atomic/atomic/amoalu/width
|
|
add wave -noupdate -expand -group lsu -color Gold /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/interlockfsm/InterlockCurrState
|
|
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
|
|
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/InterlockStall
|
|
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
|
|
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
|
|
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/WriteDataM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu.bus.dcache/dcache/cachefsm/CurrState
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/FinalWriteData
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMWayWriteEnable
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SRAMWordEnable
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/SelAdr
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/SelReplayCPURequest
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/RAdr
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush -radix unsigned /testbench/dut/core/lsu.bus.dcache/dcache/FlushAdr
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/VictimDirtyWay
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/VictimTag
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/CacheBusAdr
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/busdp/WordCount
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group flush /testbench/dut/core/lsu.bus.dcache/dcache/FlushWay
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/CacheMemWriteData
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/WayHit
|
|
add wave -noupdate -expand -group lsu -expand -group dcache /testbench/dut/core/lsu.bus.dcache/dcache/IgnoreRequest
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/SetValid}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/SetDirty}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/CacheTagMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/DirtyBits}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/ValidBits}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/DirtyBits}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/ValidBits}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/SetDirty}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/WriteWordEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/CacheTagMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way1 -expand -group Way1Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/SetValid}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/SetDirty}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/CacheTagMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/DirtyBits}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/ValidBits}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group way2 -expand -group Way2Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/SetValid}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/SetDirty}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/ClearDirty}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/VDWriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/CacheTagMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/DirtyBits}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/ValidBits}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/WriteEnable}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way3 -expand -group Way3Word3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/StoredData}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/SetValid
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/ClearValid
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/SetDirty
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu.bus.dcache/dcache/ClearDirty
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/RAdr
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/WayHit}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/Valid}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/Dirty}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way0 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[0]/ReadTag}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/WayHit}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/Valid}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/Dirty}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[1]/ReadTag}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/WayHit}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/Valid}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/Dirty}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way2 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[2]/ReadTag}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/WayHit}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/Valid}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/Dirty}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way3 {/testbench/dut/core/lsu.bus.dcache/dcache/CacheWays[3]/ReadTag}
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/WayHit
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu.bus.dcache/dcache/ReadDataWord
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimTag
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimWay
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimDirtyWay
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/core/lsu.bus.dcache/dcache/VictimDirty
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/RW
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu/IEUAdrM
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/FlushCache
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/FinalWriteData
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/ReadDataWord
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheStall
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu.bus.dcache/dcache/WayHit
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu.bus.dcache/dcache/CacheHit
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/busdp/WordCount
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheBusAdr
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheFetchLine
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheWriteLine
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheBusAck
|
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu.bus.dcache/dcache/CacheMemWriteData
|
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
|
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
|
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
|
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
|
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
|
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
|
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/AtomicAllowed
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
|
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/Match
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/FirstMatch
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/R
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/W
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/X
|
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/pmpchecker/L
|
|
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/WalkerState
|
|
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/PCF
|
|
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/HPTWAdr
|
|
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/HPTWReadPTE
|
|
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/HPTWAdr
|
|
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/PTE
|
|
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/ITLBMissF
|
|
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/DTLBMissM
|
|
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/ITLBWriteF
|
|
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/MEM_VIRTMEM/lsuvirtmem/hptw/DTLBWriteM
|
|
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu//TLBWrite
|
|
add wave -noupdate -group itlb /testbench/dut/core/ifu/ITLBMissF
|
|
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
|
add wave -noupdate -group itlb /testbench/dut/core/ifu/immu/immu/PMAInstrAccessFaultF
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HCLK
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HSELPLIC
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HADDR
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWRITE
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADY
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HTRANS
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HWDATA
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/UARTIntr
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC
|
|
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/ExtIntM
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HADDR
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWDATA
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HWRITE
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADY
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HTRANS
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADGPIO
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HRESPGPIO
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HREADYGPIO
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsIn
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsOut
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOPinsEn
|
|
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/GPIOIntr
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HCLK
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HSELCLINT
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HADDR
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWRITE
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HWDATA
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADY
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HTRANS
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADCLINT
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HRESPCLINT
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/HREADYCLINT
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM
|
|
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HCLK
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESETn
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HSELUART
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HADDR
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWRITE
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HWDATA
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADUART
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HRESPUART
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/HREADYUART
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/SIN
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DSRb
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/DCDb
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/CTSb
|
|
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/RIb
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/SOUT
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RTSb
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/DTRb
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT1b
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/OUT2b
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/INTR
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/TXRDYb
|
|
add wave -noupdate -group uart -expand -group outputs /testbench/dut/uncore/uart/uart/RXRDYb
|
|
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HCLK
|
|
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HSELUART
|
|
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HADDR
|
|
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWRITE
|
|
add wave -noupdate -group UART /testbench/dut/uncore/uart/uart/HWDATA
|
|
add wave -noupdate -group {debug trace} -expand -group mem -color Yellow /testbench/dut/core/FlushW
|
|
add wave -noupdate -group {debug trace} -expand -group mem /testbench/checkInstrM
|
|
add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/PCM
|
|
add wave -noupdate -group {debug trace} -expand -group mem /testbench/ExpectedPCM
|
|
add wave -noupdate -group {debug trace} -expand -group mem /testbench/textM
|
|
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
|
|
add wave -noupdate -group {debug trace} -expand -group wb /testbench/checkInstrW
|
|
add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
|
|
add wave -noupdate -group {debug trace} -expand -group wb /testbench/ExpectedPCW
|
|
add wave -noupdate -group {debug trace} -expand -group wb /testbench/TrapW
|
|
add wave -noupdate -group {debug trace} -expand -group wb /testbench/textW
|
|
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
|
|
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedNextPCM
|
|
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PrivilegedChangePCM
|
|
add wave -noupdate /testbench/dut/core/ifu/PCCorrectE
|
|
add wave -noupdate /testbench/dut/core/ifu/PCSrcE
|
|
add wave -noupdate /testbench/dut/core/ieu/c/BranchTakenE
|
|
add wave -noupdate /testbench/dut/core/ieu/c/BranchE
|
|
add wave -noupdate /testbench/dut/core/ifu/PCLinkE
|
|
add wave -noupdate /testbench/dut/core/ifu/PCF
|
|
add wave -noupdate /testbench/dut/uncore/uart/uart/u/LSR
|
|
add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLM
|
|
add wave -noupdate /testbench/dut/uncore/uart/uart/u/DLAB
|
|
add wave -noupdate /testbench/dut/core/ifu/temp
|
|
add wave -noupdate /testbench/dut/core/ifu/BPPredWrongM
|
|
add wave -noupdate /testbench/dut/core/ifu/InvalidateICacheM
|
|
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PCF
|
|
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
|
|
add wave -noupdate -expand -group ifu -expand -group {Bus FSM} -color Gold /testbench/dut/core/ifu/bus/busfsm/BusCurrState
|
|
add wave -noupdate -expand -group ifu -expand -group {Bus FSM} /testbench/dut/core/ifu/BusStall
|
|
add wave -noupdate -expand -group ifu -expand -group Spills /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
|
|
add wave -noupdate -expand -group ifu -expand -group Spills -color Gold /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
|
|
add wave -noupdate /testbench/dut/core/lsu.bus.dcache/dcache/VictimTag
|
|
TreeUpdate [SetDefaultTree]
|
|
WaveRestoreCursors {{Cursor 6} {5187387 ns} 1} {{Cursor 5} {88705641 ns} 0}
|
|
quietly wave cursor active 2
|
|
configure wave -namecolwidth 250
|
|
configure wave -valuecolwidth 314
|
|
configure wave -justifyvalue left
|
|
configure wave -signalnamewidth 1
|
|
configure wave -snapdistance 10
|
|
configure wave -datasetprefix 0
|
|
configure wave -rowmargin 4
|
|
configure wave -childrowmargin 2
|
|
configure wave -gridoffset 0
|
|
configure wave -gridperiod 1
|
|
configure wave -griddelta 40
|
|
configure wave -timeline 0
|
|
configure wave -timelineunits ns
|
|
update
|
|
WaveRestoreZoom {88705577 ns} {88705705 ns}
|