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cvw/fpga/src
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Rose Thompson 6a4c8667df Added new signals to ILA to debug the RVVI tracer. 
The tracer appears to be stuck and the CPU is never getting out of (into reset).
2024-05-30 16:43:25 -05:00
..
axi_sdc_controller.v Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock. 2023-10-10 17:46:12 -05:00
boot.mem Updated ROM to preload bootloader from file and infer a block ram when building for FPGA. 2023-11-18 19:15:39 -06:00
fpgaTop.v Added help option to the flash-sd script. 2023-08-22 13:37:33 -05:00
fpgaTopArtyA7.sv Added new signals to ILA to debug the RVVI tracer. 2024-05-30 16:43:25 -05:00
wallypipelinedsocwrapper.sv Merge branch 'boot' into mergeBoot 2023-07-21 17:43:45 -05:00