mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
136 lines
6.8 KiB
Systemverilog
136 lines
6.8 KiB
Systemverilog
//max function
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`define max(a,b) (((a) > (b)) ? (a) : (b))
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// constants defining different privilege modes
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// defined in Table 1.1 of the privileged spec
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localparam M_MODE = (2'b11);
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localparam S_MODE = (2'b01);
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localparam U_MODE = (2'b00);
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// Virtual Memory Constants
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localparam VPN_SEGMENT_BITS = (XLEN == 32 ? 32'd10 : 32'd9);
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localparam VPN_BITS = (XLEN==32 ? (2*VPN_SEGMENT_BITS) : (4*VPN_SEGMENT_BITS));
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localparam PPN_BITS = (XLEN==32 ? 32'd22 : 32'd44);
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localparam PA_BITS = (XLEN==32 ? 32'd34 : 32'd56);
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localparam SVMODE_BITS = (XLEN==32 ? 32'd1 : 32'd4);
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localparam ASID_BASE = (XLEN==32 ? 32'd22 : 32'd44);
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localparam ASID_BITS = (XLEN==32 ? 32'd9 : 32'd16);
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// constants to check SATP_MODE against
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// defined in Table 4.3 of the privileged spec
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localparam NO_TRANSLATE = 4'd0;
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localparam SV32 = 4'd1;
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localparam SV39 = 4'd8;
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localparam SV48 = 4'd9;
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// macros to define supported modes
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localparam logic I_SUPPORTED = (!E_SUPPORTED);
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localparam logic A_SUPPORTED = (ZAAMO_SUPPORTED & ZALRSC_SUPPORTED);
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localparam logic B_SUPPORTED = ((ZBA_SUPPORTED & ZBB_SUPPORTED & ZBS_SUPPORTED));
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localparam logic C_SUPPORTED = ZCA_SUPPORTED & (D_SUPPORTED ? ZCD_SUPPORTED : 1) & (F_SUPPORTED ? ((XLEN == 32) ? ZCF_SUPPORTED : 1) : 1);
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localparam logic ZKN_SUPPORTED = (ZBKB_SUPPORTED & ZBKC_SUPPORTED & ZBKX_SUPPORTED & ZKND_SUPPORTED & ZKNE_SUPPORTED & ZKNH_SUPPORTED);
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// Configure MISA based on supported extensions
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localparam MISA = {6'b0, 5'b0, U_SUPPORTED, 1'b0, S_SUPPORTED, 1'b0, Q_SUPPORTED, 3'b0, M_SUPPORTED, 3'b0, I_SUPPORTED, 2'b0,
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F_SUPPORTED, E_SUPPORTED, D_SUPPORTED, C_SUPPORTED, B_SUPPORTED, A_SUPPORTED};
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// logarithm of XLEN, used for number of index bits to select
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localparam LOG_XLEN = (XLEN == 32 ? 32'd5 : 32'd6);
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// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
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localparam PMPCFG_ENTRIES = (PMP_ENTRIES/32'd8);
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// Floating point constants for Quad, Double, Single, and Half precisions
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// Lim: I've made some of these 64 bit to avoid width warnings.
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// If errors crop up, try downsizing back to 32.
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localparam Q_LEN = 32'd128;
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localparam Q_NE = 32'd15;
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localparam Q_NF = 32'd112;
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localparam Q_BIAS = 32'd16383;
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localparam Q_FMT = 2'd3;
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localparam D_LEN = 32'd64;
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localparam D_NE = 32'd11;
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localparam D_NF = 32'd52;
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localparam D_BIAS = 32'd1023;
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localparam D_FMT = 2'd1;
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localparam S_LEN = 32'd32;
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localparam S_NE = 32'd8;
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localparam S_NF = 32'd23;
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localparam S_BIAS = 32'd127;
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localparam S_FMT = 2'd0;
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localparam H_LEN = 32'd16;
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localparam H_NE = 32'd5;
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localparam H_NF = 32'd10;
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localparam H_BIAS = 32'd15;
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localparam H_FMT = 2'd2;
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// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits (for longest format supported)
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localparam FLEN = Q_SUPPORTED ? Q_LEN : D_SUPPORTED ? D_LEN : S_LEN;
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localparam NE = Q_SUPPORTED ? Q_NE : D_SUPPORTED ? D_NE : S_NE;
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localparam NF = Q_SUPPORTED ? Q_NF : D_SUPPORTED ? D_NF : S_NF;
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localparam FMT = Q_SUPPORTED ? 2'd3 : D_SUPPORTED ? 2'd1 : 2'd0;
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localparam BIAS = Q_SUPPORTED ? Q_BIAS : D_SUPPORTED ? D_BIAS : S_BIAS;
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localparam LOGFLEN = $clog2(FLEN);
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// Floating point constants needed for FPU paramerterization
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// LEN1/NE1/NF1/FNT1 is the size of the second longest supported format
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localparam FPSIZES = (32)'(Q_SUPPORTED)+(32)'(D_SUPPORTED)+(32)'(F_SUPPORTED)+(32)'(ZFH_SUPPORTED);
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localparam FMTBITS = (32)'(FPSIZES>=3)+1;
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localparam LEN1 = (FLEN > D_LEN) ? D_LEN : (FLEN > S_LEN) ? S_LEN : H_LEN;
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localparam NE1 = (FLEN > D_LEN) ? D_NE : (FLEN > S_LEN) ? S_NE : H_NE;
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localparam NF1 = (FLEN > D_LEN) ? D_NF : (FLEN > S_LEN) ? S_NF : H_NF;
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localparam FMT1 = (FLEN > D_LEN) ? 2'd1 : (FLEN > S_LEN) ? 2'd0 : 2'd2;
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localparam BIAS1 = (FLEN > D_LEN) ? D_BIAS : (FLEN > S_LEN) ? S_BIAS : H_BIAS;
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// LEN2 etc is the size of the third longest supported format
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localparam LEN2 = (LEN1 > S_LEN) ? S_LEN : H_LEN;
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localparam NE2 = (LEN1 > S_LEN) ? S_NE : H_NE;
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localparam NF2 = (LEN1 > S_LEN) ? S_NF : H_NF;
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localparam FMT2 = (LEN1 > S_LEN) ? 2'd0 : 2'd2;
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localparam BIAS2 = (LEN1 > S_LEN) ? S_BIAS : H_BIAS;
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// divider r and rk (bits per digit, bits per cycle)
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localparam LOGR = $clog2(RADIX); // r = log(R) bits per digit
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localparam RK = LOGR*DIVCOPIES; // r*k bits per cycle generated
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// intermediate division parameters not directly used in fdivsqrt hardware
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localparam FPDIVMINb = NF + 2; // minimum length of fractional part: Nf result bits + guard and round bits + 1 extra bit to allow sqrt being shifted right
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localparam DIVMINb = ((FPDIVMINb<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVMINb; // minimum fractional bits b = max(XLEN, FPDIVMINb)
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localparam RESBITS = DIVMINb + LOGR; // number of bits in a result: r integer + b fractional
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// division constants
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localparam FPDUR = (RESBITS-1)/RK + 1 ; // ceiling((r+b)/rk)
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localparam DIVb = FPDUR*RK - LOGR; // divsqrt fractional bits, so total number of bits is a multiple of rk after r integer bits
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localparam DURLEN = $clog2(FPDUR); // enough bits to count the duration
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localparam DIVBLEN = $clog2(DIVb+1); // enough bits to count number of fractional bits + 1 integer bit
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// largest length in IEU/FPU
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localparam BASECVTLEN = `max(XLEN, NF); // convert length excluding Zfa fcvtmod.w.d
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localparam CVTLEN = (ZFA_SUPPORTED & D_SUPPORTED) ? `max(BASECVTLEN, 32'd84) : BASECVTLEN; // fcvtmod.w.d needs at least 32+52 because a double with 52 fractional bits might be into upper bits of 32 bit word
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localparam LLEN = `max($unsigned(FLEN), $unsigned(XLEN));
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localparam LOGCVTLEN = $unsigned($clog2(CVTLEN+1));
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// size of FMA output
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localparam FMALEN = 3*NF + 6;
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// NORMSHIFTSIZE is the bits out of the normalization shifter
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// RV32F: max(32+23+1, 2(23)+4, 3(23)+6) = 3*23+6 = 75
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// RV64F: max(64+23+1, 64 + 23 + 2, 3*23+6) = 89
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// RV64D: max(84+52+1, 64+52+2, 3*52+6) = 162
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// *** DH 5/10/24 testbench_fp f_ieee_div_2_1_rv64gc cvtint was failing for fcvt.lu.s
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// with CVTLEN+NF+1. Changing to CVTLEN+NF+1+2 fixes failures
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// This same failure occurred for any test with IDIV_ON_FPU = 0, FLEN=32, XLEN=64
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// because NORMSHIFTSZ becomes limited by convert rather than divider
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// The two extra bits are necessary because shiftcorrection dropped them for fcvt.
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// May be possible to remove these two bits by modifying shiftcorrection
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//localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1+2), (DIVb + 1 + NF + 1)), (FMALEN + 2));
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localparam NORMSHIFTSZ = `max(`max((CVTLEN+NF+1), (DIVb + 1 + NF + 1)), (FMALEN + 2));
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localparam LOGNORMSHIFTSZ = ($clog2(NORMSHIFTSZ)); // log_2(NORMSHIFTSZ)
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// Disable spurious Verilator warnings
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/* verilator lint_off STMTDLY */
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/* verilator lint_off ASSIGNDLY */
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/* verilator lint_off PINCONNECTEMPTY */
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