cvw/pipelined/src/privileged
2022-04-25 19:17:29 +00:00
..
csr.sv Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
csrc.sv Added back the instret counter to ILA. 2022-04-17 18:44:07 -05:00
csri.sv Fixed bug with CSRRS/CSRRC for MIP/SIP 2022-04-03 20:18:25 +00:00
csrm.sv Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields 2022-04-25 14:49:00 +00:00
csrs.sv Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change. 2022-02-15 19:20:41 +00:00
csrsr.sv fixed initial value, timing on fs bits changing after floating point instruction 2022-04-25 19:17:29 +00:00
csru.sv Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv 2022-01-20 16:39:54 -06:00
privdec.sv First implementation of WFI timeout wait 2022-04-17 17:20:35 +00:00
privileged.sv Added MTINST hardwired to 0, and added timeout of U-mode WFI 2022-04-24 20:00:02 +00:00
trap.sv Fixed InstrMisalignedFaultM mtval 2022-04-24 17:31:30 +00:00