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99 lines
3.5 KiB
Systemverilog
99 lines
3.5 KiB
Systemverilog
///////////////////////////////////////////
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// comparator.sv
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//
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// Written: David_Harris@hmc.edu 8 December 2021
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// Modified:
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//
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// Purpose: Branch comparison
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module comparator #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] a, b,
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output logic [2:0] flags);
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logic [WIDTH-1:0] bbar, diff;
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logic carry, eq, neg, overflow, lt, ltu;
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// NOTE: This can be replaced by some faster logic optimized
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// to just compute flags and not the difference.
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// subtraction
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assign bbar = ~b;
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assign {carry, diff} = a + bbar + 1;
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// condition code flags based on add/subtract output
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assign eq = (diff == 0);
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assign neg = diff[WIDTH-1];
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// overflow occurs when the numbers being subtracted have the opposite sign
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// and the result has the opposite sign fron the first
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assign overflow = (a[WIDTH-1] ^ b[WIDTH-1]) & (a[WIDTH-1] ^ diff[WIDTH-1]);
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assign lt = neg ^ overflow;
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assign ltu = ~carry;
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// assign flags = {eq, lt, ltu};
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/* verilator lint_off UNOPTFLAT */
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// prefix implementation
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localparam levels=$clog2(WIDTH);
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genvar i;
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genvar level;
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logic [WIDTH-1:0] ee[levels:0];
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logic [WIDTH-1:0] ll[levels:0];
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logic eq2, lt2, ltu2;
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// Bitwise logic
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for (i=0; i<WIDTH; i++) begin
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assign ee[0][i] = a[i] ~^ b[i]; // bitwise equality
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assign ll[0][i] = ~a[i] & b[i]; // bitwise less than unsigned
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end
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// Recursion
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for (level = 1; level<=levels; level++) begin
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for (i=0; i<WIDTH/(2**level); i++) begin
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assign ee[level][i] = ee[level-1][i*2+1] & ee[level-1][i*2];
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assign ll[level][i] = ll[level-1][i*2+1] | ee[level-1][i*2+1] & ll[level-1][i*2];
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end
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end
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// Output logic
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assign eq2 = ee[levels][0];
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assign ltu2 = ll[levels][0];
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assign lt2 = ltu2 & ~ll[0][WIDTH-1] | a[WIDTH-1] & ~b[WIDTH-1];
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always_comb begin
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assert (eq2 === eq) else $display("a %h b %h eq %b eq2 %b\n", a, b, eq, eq2);
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assert (ltu2 === ltu) else $display("a %h b %h ltu %b ltu2 %b\n", a, b, ltu, ltu2);
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assert (lt2 === lt) else $display("a %h b %h lt %b lt2 %b ltu2 %b L31 %b\n", a, b, lt, lt2, ltu2, ll[0][WIDTH-1]);
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end
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assign flags = {eq2, lt2, ltu2};
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/* verilator lint_on UNOPTFLAT */
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endmodule
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