Ross Thompson de4ea16d32 Merge branch 'main' into fpga		2021-10-20 16:24:55 -05:00
..
csr.sv	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
csrc.sv	Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.	2021-09-15 13:14:00 -04:00
csri.sv	fixed bug where M mode was sensitive to S mode traps	2021-09-07 19:14:39 -04:00
csrm.sv	Merge branch 'main' into fpga	2021-10-20 16:24:55 -05:00
csrn.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
csrs.sv	Merge branch 'main' into fpga	2021-10-20 16:24:55 -05:00
csrsr.sv	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
csru.sv	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
privdec.sv	Implemented TSR, TW, TVM, MXR status bits	2021-07-06 01:32:05 -04:00
privileged.sv	Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.	2021-08-23 15:46:17 -05:00
trap.sv	Added debugging directives to system verilog.	2021-09-27 13:57:46 -05:00