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73 lines
3.6 KiB
Systemverilog
73 lines
3.6 KiB
Systemverilog
///////////////////////////////////////////
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// divshiftcalc.sv
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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//
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// Purpose: Division shift calculation
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module divshiftcalc import cvw::*; #(parameter cvw_t P) (
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input logic [P.DIVb:0] DivQm, // divsqrt significand
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input logic [P.NE+1:0] DivQe, // divsqrt exponent
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output logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt, // divsqrt shift amount
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output logic [P.NORMSHIFTSZ-1:0] DivShiftIn, // divsqrt shift input
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output logic DivResSubnorm, // is the divsqrt result subnormal
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output logic DivSubnormShiftPos // is the subnormal shift amount positive
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);
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logic [P.LOGNORMSHIFTSZ-1:0] NormShift; // normalized result shift amount
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logic [P.LOGNORMSHIFTSZ-1:0] DivSubnormShiftAmt; // subnormal result shift amount (killed if negitive)
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logic [P.NE+1:0] DivSubnormShift; // subnormal result shift amount
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// is the result subnormal
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// if the exponent is 1 then the result needs to be normalized then the result is Subnormalizes
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assign DivResSubnorm = DivQe[P.NE+1]|(~|DivQe[P.NE+1:0]);
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// if the result is subnormal
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// 00000000x.xxxxxx... Exp = DivQe
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// .00000000xxxxxxx... >> NF+1 Exp = DivQe+NF+1
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// .00xxxxxxxxxxxxx... << DivQe+NF+1 Exp = +1
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// .0000xxxxxxxxxxx... >> 1 Exp = 1
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// Left shift amount = DivQe+NF+1-1
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assign DivSubnormShift = (P.NE+2)'(P.NF)+DivQe;
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assign DivSubnormShiftPos = ~DivSubnormShift[P.NE+1];
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// if the result is normalized
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// 00000000x.xxxxxx... Exp = DivQe
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// .00000000xxxxxxx... >> NF+1 Exp = DivQe+NF+1
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// 00000000.xxxxxxx... << NF Exp = DivQe+1
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// 00000000x.xxxxxx... << NF Exp = DivQe (extra shift done afterwards)
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// 00000000xx.xxxxx... << 1? Exp = DivQe-1 (determined after)
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// inital Left shift amount = NF
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// shift one more if the it's a minimally redundent radix 4 - one entire cycle needed for integer bit
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assign NormShift = (P.LOGNORMSHIFTSZ)'(P.NF);
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// if the shift amount is negitive then don't shift (keep sticky bit)
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// need to multiply the early termination shift by LOGR*DIVCOPIES = left shift of log2(LOGR*DIVCOPIES)
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assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0;
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assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift;
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// pre-shift the divider result for normalization
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assign DivShiftIn = {{P.NF{1'b0}}, DivQm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}};
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endmodule
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