Thomas Fleming dc8a165806 Add lru algorithm to TLB		2021-04-13 13:37:24 -04:00
..
cache	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-03-30 15:25:07 -04:00
dmem	Implement support for superpages	2021-04-08 02:44:59 -04:00
ebu	Implement support for superpages	2021-04-08 02:44:59 -04:00
fpu	fixed FPU lint warnings	2021-04-08 18:03:21 +00:00
generic	change flop in ahb controller to use normal flop module	2021-03-10 19:14:02 +00:00
hazard	Partial fix to the integer divide stall issue.	2021-04-02 15:32:15 -05:00
ieu	Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.	2021-04-02 06:27:37 -05:00
ifu	Implement support for superpages	2021-04-08 02:44:59 -04:00
mmu	Add lru algorithm to TLB	2021-04-13 13:37:24 -04:00
muldiv	Partial fix to the integer divide stall issue.	2021-04-02 15:32:15 -05:00
privileged	Cause an Illegal Instruction Exception when attempting to write readonly CSRs	2021-04-08 05:12:54 -04:00
tlb_toy	Install tlb into ifu	2021-03-04 03:11:34 -05:00
uncore	declare memread signal	2021-04-05 08:13:01 -04:00
wally	Implement support for superpages	2021-04-08 02:44:59 -04:00