mirror of
https://github.com/openhwgroup/cvw
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72 lines
2.0 KiB
ArmAsm
72 lines
2.0 KiB
ArmAsm
///////////////////////////////////////////
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// csrwrites.S
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//
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// Written: David_Harris@hmc.edu 21 March 2023
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//
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// Purpose: Test writes to CSRs
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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li t0, -5
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csrw stimecmp, t0 # initialize so ImperasDV agrees
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csrrw t0, stimecmp, t0
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csrrw t0, satp, zero
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csrrw t0, stvec, zero
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csrrw t0, sscratch, zero
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li t0, -2
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csrrw t1, menvcfg, t0
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csrrw t2, senvcfg, t0
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# Test writing to TIME CSR
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csrw time, zero
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# testing FIOM with different privilege modes
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# setting environment config (to both 1 and 0) in each privilege mode
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csrsi menvcfg, 1
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li a0, 1
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ecall # enter supervisor mode
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li a0, 0
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ecall # enter user mode
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li a0, 1
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ecall # enter supervisor mode
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csrsi senvcfg, 1
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li a0, 0
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ecall # enter user mode
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li a0, 3
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ecall # enter machine mode
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csrci menvcfg, 1
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li a0, 1
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ecall # enter supervisor mode
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li a0, 0
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ecall # enter user mode
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j done
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