mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Bumps [addins/riscv-dv](https://github.com/google/riscv-dv) from `f0c570d` to `7e54b67`.
- [Commits](
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berkeley-softfloat-3@3b70b5d814 | ||
berkeley-testfloat-3@03c13d21db | ||
branch-predictor-simulator@3e424e902f | ||
coremark@f3e8f2e094 | ||
cvw-arch-verif@b31c5c25da | ||
embench-iot@54fd9a0f10 | ||
riscv-arch-test@eeffdf802c | ||
riscv-dv@7e54b678ab | ||
verilog-ethernet@c180b22ed5 | ||
vivado-boards@d1898bd01f | ||
README.md | ||
sparse-checkout |
verilog-ethernet contains many ethernet devices. Wally's synthesizable RVVI interface only requires a small subset of these files. To do a sparse checkout of this repo copy sparse-checkout to cvw/.git/modules/addins/verilog-ethernet/info This will make the working directory only contain the necessary files.