mirror of
https://github.com/openhwgroup/cvw
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67 lines
1.4 KiB
ArmAsm
67 lines
1.4 KiB
ArmAsm
// example.s
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// David_Harris@hmc.edu 5 December 2021
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.section .text.init
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//.globl rvtest_entry_point
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//rvtest_entry_point:
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.globl main
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main:
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li a0, 42
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self_loop:
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j self_loop
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.end
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/*
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#include "model_test.h"
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#include "arch_test.h"
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RVTEST_ISA("RV32I")
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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#ifdef TEST_CASE_1
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RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*);def TEST_CASE_1=True;",add)
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RVTEST_SIGBASE( x3,signature_x3_1)
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inst_0:
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// rs2 == rd != rs1, rs1==x4, rs2==x24, rd==x24, rs1_val > 0 and rs2_val > 0, rs2_val == 1, rs1_val == (2**(xlen-1)-1), rs1_val != rs2_val, rs1_val == 2147483647
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// opcode: add ; op1:x4; op2:x24; dest:x24; op1val:0x7fffffff; op2val:0x1
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TEST_RR_OP(add, x24, x4, x24, 0x80000000, 0x7fffffff, 0x1, x3, 0, x18)
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80000000 <rvtest_entry_point>:
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.section .text.init
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.globl rvtest_entry_point
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rvtest_entry_point:
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RVMODEL_BOOT
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RVTEST_CODE_BEGIN
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80000000: feedc0b7 lui ra,0xfeedc
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8
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80003220 <rvtest_code_end>:
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#endif
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RVTEST_CODE_END
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RVMODEL_HALT
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80003220: 00408093 addi ra,ra,4
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80003224: 00100093 li ra,1
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80003228 <write_tohost>:
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80003228: 00001f17 auipc t5,0x1
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8000322c: dc1f2c23 sw ra,-552(t5) # 80004000 <tohost>
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80003230 <self_loop>:
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80003230: 0000006f j 80003230 <self_loop>
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80003234: 0000 unimp
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...
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*/ |