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https://github.com/openhwgroup/cvw
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59 lines
1.5 KiB
ArmAsm
59 lines
1.5 KiB
ArmAsm
///////////////////////////////////////////////////////////////////////
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// riscv.S
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//
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// Written: Jaocb Pease jacob.pease@okstate.edu 7/22/2024
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//
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// Purpose: Basic utility functions for reading registers
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//
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//
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the
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// “License”); you may not use this file except in compliance with the
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// License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work
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// distributed under the License is distributed on an “AS IS” BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
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// implied. See the License for the specific language governing
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// permissions and limitations under the License.
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///////////////////////////////////////////////////////////////////////
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.section .text
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.globl read_mcycle
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.type read_mcycle, @function
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read_mcycle:
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csrr a0, mcycle
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ret
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.section .text
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.globl get_ra
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.type get_ra, @function
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get_ra:
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mv a0, ra
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ret
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.section .text
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.globl set_status_fs
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.type set_status_fs, @function
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set_status_fs:
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lui t1, 0x6
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csrs mstatus, t1
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ret
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.section .text
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.globl clear_status_fs
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.type clear_status_fs, @function
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clear_status_fs:
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lui t1, 0x6
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csrc mstatus, t1
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ret
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