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46 lines
2.0 KiB
Makefile
46 lines
2.0 KiB
Makefile
# Wally Coremark Makefile
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# Daniel Torres & David Harris 28 July 2022
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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PORT_DIR = $(CURDIR)/riscv64-baremetal
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cmbase=../../addins/coremark
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work_dir= ../../benchmarks/coremark/work
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XLEN ?=64
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sources=$(cmbase)/core_main.c $(cmbase)/core_list_join.c $(cmbase)/coremark.h \
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$(cmbase)/core_matrix.c $(cmbase)/core_state.c $(cmbase)/core_util.c \
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$(PORT_DIR)/core_portme.h $(PORT_DIR)/core_portme.c $(PORT_DIR)/core_portme.mak \
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$(PORT_DIR)/crt.S $(PORT_DIR)/encoding.h $(PORT_DIR)/util.h $(PORT_DIR)/syscalls.c
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ABI := $(if $(findstring "64","$(XLEN)"),lp64,ilp32)
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ARCH := rv$(XLEN)im
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PORT_CFLAGS = -g -mabi=$(ABI) -march=$(ARCH) -static -falign-functions=16 \
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-mbranch-cost=1 -DSKIP_DEFAULT_MEMSET -mtune=sifive-3-series -O3 -finline-functions -falign-jumps=4 \
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-fno-delete-null-pointer-checks -fno-rename-registers --param=loop-max-datarefs-for-datadeps=0 \
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-funroll-all-loops --param=uninlined-function-insns=8 -fno-tree-vrp -fwrapv -fipa-pta \
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-nostdlib -nostartfiles -ffreestanding -mstrict-align \
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-DTOTAL_DATA_SIZE=2000 -DMAIN_HAS_NOARGC=1 -DPERFORMANCE_RUN=1 -DITERATIONS=10 -DXLEN=$(XLEN)
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all: $(work_dir)/coremark.bare.riscv.elf.memfile
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run:
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(cd ../../sim && (time vsim -c -do "do wally-batch.do rv$(XLEN)gc coremark" 2>&1 | tee $(work_dir)/coremark.sim.log))
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cd ../benchmarks/coremark/
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# KMG: added post processing script to give out branch miss proportion along with other stats to the coremark test
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python3 coremark-postprocess.py
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$(work_dir)/coremark.bare.riscv.elf.memfile: $(work_dir)/coremark.bare.riscv
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riscv64-unknown-elf-objdump -D $< > $<.elf.objdump
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riscv64-unknown-elf-elf2hex --bit-width $(XLEN) --input $< --output $@
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extractFunctionRadix.sh $<.elf.objdump
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$(work_dir)/coremark.bare.riscv: $(sources) Makefile
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make -C $(cmbase) PORT_DIR=$(PORT_DIR) compile RISCV=$(RISCV)/riscv-gnu-toolchain XCFLAGS="$(PORT_CFLAGS)"
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mkdir -p $(work_dir)
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mv $(cmbase)/coremark.bare.riscv $(work_dir)
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.PHONY: clean
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clean:
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rm -f $(work_dir)/*
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