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https://github.com/openhwgroup/cvw
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79 lines
2.8 KiB
Plaintext
79 lines
2.8 KiB
Plaintext
###########################################
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## derivlist.txt
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## Wally Derivative Configuration List
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##
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## Written: David_Harris@hmc.edu
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## Created: 29 January 2024
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## Modified:
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##
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## Purpose: Used by sim/make deriv to generate derivative configurations
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## in config/deriv that are variants of the base configurations.
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##
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## A component of the CORE-V-WALLY configurable RISC-V project.
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## https://github.com/openhwgroup/cvw
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##
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## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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##
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## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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##
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## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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## except in compliance with the License, or, at your option, the Apache License version 2.0. You
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## may obtain a copy of the License at
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##
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## https:##solderpad.org/licenses/SHL-2.1/
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##
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## Unless required by applicable law or agreed to in writing, any work distributed under the
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## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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## either express or implied. See the License for the specific language governing permissions
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## and limitations under the License.
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################################################################################################
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# Format:
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# begin a derivative with "deriv <derivative name> <base configuration name> <inherited config name>
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# Followed by a list of parameters and their new value in the derivative configuration
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# All other parameter values are inherited from the original configuration
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# If <inherited config name> is not empty, all the list of parameter changes in the inherited
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# configuration are also applied to this configuration
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# buildroot is used for the Linux boot
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deriv buildroot rv64gc
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RESET_VECTOR 64'h1000
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UNCORE_RAM_RANGE 64'h0FFFFFFF
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UNCORE_RAM_PRELOAD 1
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GPIO_LOOPBACK_TEST 0
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SPI_LOOBACK_TEST 0
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UART_PRESCALE 0
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PLIC_NUM_SRC 32'd53
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# fpga is used for FPGA hardware. It adds the SDC and DDR (EXT_MEM)
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deriv fpga rv64gc buildroot
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BOOTROM_PRELOAD 1
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UNCORE_RAM_BASE 64'h2000
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UNCORE_RAM_RANGE 64'hFFF
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EXT_MEM_SUPPORTED 1
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EXT_MEM_BASE 64'h80000000
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EXT_MEM_RANGE 64'h0FFFFFFF
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SDC_SUPPORTED 1
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PLIC_SDC_ID 32'd20
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BPRED_SIZE 32'd12
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# The syn configurations are trimmed down for faster synthesis.
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deriv syn_rv32e rv32e
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DTIM_RANGE 32'h1FF
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IROM_RANGE 32'h1FF
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BOOTROM_RANGE 32'h1FF
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UNCORE_RAM_RANGE 32'h1FF
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BOOTROM_RANGE 32'h1FF
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WAYSIZEINBYTES 32'd512
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NUMWAYS 32'd1
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BPRED_SIZE 32'd5
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BTB_SIZE 32'd5
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# The other syn configurations have the same trimming
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deriv syn_rv32i rv32i syn_rv32e
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deriv syn_rv32imc rv32imc syn_rv32e
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deriv syn_rv32gc rv32gc syn_rv32e
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deriv syn_rv64i rv64i syn_rv32e
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deriv syn_rv64gc rv64gc syn_rv32e
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