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https://github.com/openhwgroup/cvw
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73 lines
1.3 KiB
Systemverilog
Executable File
73 lines
1.3 KiB
Systemverilog
Executable File
module tb;
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logic [52:0] d, n;
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logic reset;
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logic [63:0] q, qm, qp, rega_out, regb_out, regc_out;
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logic [127:0] regr_out;
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logic start;
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logic error;
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logic op_type;
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logic done;
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logic load_rega;
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logic load_regb;
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logic load_regc;
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logic load_regr;
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logic [1:0] sel_muxa;
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logic [1:0] sel_muxb;
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logic sel_muxr;
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logic clk;
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integer handle3;
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integer desc3;
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divconv dut (q, qm, qp, rega_out, regb_out, regc_out, regr_out,
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d, n, sel_muxa, sel_muxb, sel_muxr, reset, clk,
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load_rega, load_regb, load_regc, load_regr);
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fsm control (done, load_rega, load_regb, load_regc, load_regr,
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sel_muxa, sel_muxb, sel_muxr,
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clk, reset, start, error, op_type);
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initial
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begin
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clk = 1'b1;
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forever #5 clk = ~clk;
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end
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initial
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begin
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handle3 = $fopen("divconvDP.out");
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#700 $finish;
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end
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always
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begin
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desc3 = handle3;
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#5 $fdisplay(desc3, "%b %b %b | %h %h | %h %h %h | %h %h %h %h", sel_muxa,
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sel_muxb, sel_muxr, d, n, q, qm, qp, rega_out, regb_out, regc_out, regr_out);
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end
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initial
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begin
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#0 start = 1'b0;
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#0 n = 53'h1C_0000_0000_0000; // 1.75
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#0 d = 53'h1E_0000_0000_0000; // 1.875
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#0 reset = 1'b1;
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#20 reset = 1'b0;
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#20 start = 1'b1;
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#40 start = 1'b0;
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end
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endmodule // tb
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