Ross Thompson d4de8a54a2 Icache now uses physical lenght bits rather than XLEN.		2021-06-18 12:02:59 -05:00
..
cache-sram.sv	A few more cache fixes	2021-04-13 01:07:40 -04:00
dmapped.sv	Eliminated extra register and fixed ports to icache.	2021-05-03 12:04:54 -05:00
icache.sv	Icache now uses physical lenght bits rather than XLEN.	2021-06-18 12:02:59 -05:00
ICacheCntrl.sv	Icache now uses physical lenght bits rather than XLEN.	2021-06-18 12:02:59 -05:00
ICacheMem.sv	Icache now uses physical lenght bits rather than XLEN.	2021-06-18 12:02:59 -05:00
sram1rw.sv	Reduced icache to 1 port memory.	2021-05-03 14:47:49 -05:00