mirror of
https://github.com/openhwgroup/cvw
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46 lines
1.4 KiB
Perl
Executable File
46 lines
1.4 KiB
Perl
Executable File
#!/usr/bin/perl -w
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# vclean.pl
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# David_Harris@hmc.edu 7 December 2023
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# Identifies unused signals in Verilog files
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# verilator should do this, but it also reports partially used signals
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use strict;
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for (my $i=0; $i<=$#ARGV; $i++) {
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my $fname = $ARGV[$i];
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&clean($fname);
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}
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sub clean {
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my $fname = shift;
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# printf ("Cleaning $fname\n");
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open(FILE, $fname) || die("Can't read $fname");
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# my $incomment = 0;
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my @allsigs;
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while (<FILE>) {
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if (/typedef/) { } # skip typedefs
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elsif (/logic (.*)/) { # found signal declarations
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my $siglist = $1;
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$siglist =~ s/\/\/.*//; # trim off everything after //
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# print ("Logic: $siglist\n");
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$siglist =~ s/\[[^\]]*\]//g; # trim off everything in brackets
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$siglist =~ s/\s//g; # trim off white space
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# print ("Logic Trimmed: $siglist\n");
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my @sigs = split(/[,;)]/, $siglist);
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# print ("Logic parsed: @sigs\n");
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push(@allsigs, @sigs);
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}
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}
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# print("Signals: @allsigs\n");
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foreach my $sig (@allsigs) {
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if ($sig eq "") { last }; # skip empty signals
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# print("Searching for '$sig'\n");
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my $hits = `grep -c $sig $fname`;
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# print(" Signal $sig appears $hits times\n");
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if ($hits < 2) {
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printf("$sig not used in $fname\n");
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}
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}
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} |