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124 lines
8.1 KiB
Systemverilog
124 lines
8.1 KiB
Systemverilog
///////////////////////////////////////////
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// trap.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified: dottolia@hmc.edu 14 April 2021: Add support for vectored interrupts
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//
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// Purpose: Handle Traps: Exceptions and Interrupts
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//
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// Documentation: RISC-V System on Chip Design Chapter 5 (Figure 5.9)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module trap import cvw::*; #(parameter cvw_t P) (
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input logic reset,
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input logic InstrMisalignedFaultM, InstrAccessFaultM, HPTWInstrAccessFaultM, HPTWInstrPageFaultM, IllegalInstrFaultM,
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input logic BreakpointFaultM, LoadMisalignedFaultM, StoreAmoMisalignedFaultM,
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input logic LoadAccessFaultM, StoreAmoAccessFaultM, EcallFaultM, InstrPageFaultM,
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input logic LoadPageFaultM, StoreAmoPageFaultM, // various trap sources
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input logic wfiM, wfiW, // wait for interrupt instruction
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input logic [1:0] PrivilegeModeW, // current privilege mode
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input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW, // interrupt pending, enabled, and delegate CSRs
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input logic [15:0] MEDELEG_REGW, // exception delegation SR
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input logic STATUS_MIE, STATUS_SIE, // machine/supervisor interrupt enables
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input logic InstrValidM, // current instruction is valid, not flushed
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input logic CommittedM, CommittedF, // LSU/IFU has committed to a bus operation that can't be interrupted
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output logic TrapM, // Trap is occurring
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output logic InterruptM, // Interrupt is occurring
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output logic ExceptionM, // exception is occurring
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output logic IntPendingM, // Interrupt is pending, might occur if enabled
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output logic DelegateM, // Delegate trap to supervisor handler
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output logic [3:0] CauseM // trap cause
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);
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logic MIntGlobalEnM, SIntGlobalEnM; // Global interupt enables
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logic Committed; // LSU or IFU has committed to a bus operation that can't be interrupted
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logic BothInstrAccessFaultM, BothInstrPageFaultM; // instruction or HPTW ITLB fill caused an Instruction Access Fault
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logic [11:0] PendingIntsM, ValidIntsM, EnabledIntsM; // interrupts are pending, valid, or enabled
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///////////////////////////////////////////
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// Determine pending enabled interrupts
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// interrupt if any sources are pending
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// & with a M stage valid bit to avoid interrupts from interrupt a nonexistent flushed instruction (in the M stage)
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// & with ~CommittedM to make sure MEPC isn't chosen so as to rerun the same instr twice
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///////////////////////////////////////////
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assign MIntGlobalEnM = (PrivilegeModeW != P.M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9
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assign SIntGlobalEnM = (PrivilegeModeW == P.U_MODE) | ((PrivilegeModeW == P.S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
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assign PendingIntsM = MIP_REGW & MIE_REGW;
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assign IntPendingM = |PendingIntsM;
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assign Committed = CommittedM | CommittedF;
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assign EnabledIntsM = (MIntGlobalEnM ? PendingIntsM & ~MIDELEG_REGW : '0) | (SIntGlobalEnM ? PendingIntsM & MIDELEG_REGW : '0);
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assign ValidIntsM = Committed ? '0 : EnabledIntsM;
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assign InterruptM = (|ValidIntsM) & InstrValidM & (~wfiM | wfiW); // suppress interrupt if the memory system has partially processed a request. Delay interrupt until wfi is in the W stage.
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// wfiW is to support possible but unlikely back to back wfi instructions. wfiM would be high in the M stage, while also in the W stage.
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assign DelegateM = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) &
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(PrivilegeModeW == P.U_MODE | PrivilegeModeW == P.S_MODE);
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///////////////////////////////////////////
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// Trigger Traps
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// According to RISC-V Spec Section 1.6, exceptions are caused by instructions. Interrupts are external asynchronous.
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// Traps are the union of exceptions and interrupts.
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///////////////////////////////////////////
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assign BothInstrAccessFaultM = InstrAccessFaultM | HPTWInstrAccessFaultM;
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assign BothInstrPageFaultM = InstrPageFaultM | HPTWInstrPageFaultM;
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// coverage off -item e 1 -fecexprrow 2
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// excludes InstrMisalignedFaultM from coverage of this line, since misaligned instructions cannot occur in rv64gc.
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assign ExceptionM = InstrMisalignedFaultM | BothInstrAccessFaultM | IllegalInstrFaultM |
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LoadMisalignedFaultM | StoreAmoMisalignedFaultM |
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BothInstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM |
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BreakpointFaultM | EcallFaultM |
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LoadAccessFaultM | StoreAmoAccessFaultM;
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// coverage on
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assign TrapM = (ExceptionM & ~CommittedF) | InterruptM; // *** RT: review this additional ~CommittedF with DH and update priv chapter.
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///////////////////////////////////////////
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// Cause priority defined in privileged spec
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///////////////////////////////////////////
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always_comb
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if (reset) CauseM = 4'd0; // hard reset 3.3
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else if (ValidIntsM[11]) CauseM = 4'd11; // Machine External Int
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else if (ValidIntsM[3]) CauseM = 4'd3; // Machine Sw Int
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else if (ValidIntsM[7]) CauseM = 4'd7; // Machine Timer Int
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else if (ValidIntsM[9]) CauseM = 4'd9; // Supervisor External Int
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else if (ValidIntsM[1]) CauseM = 4'd1; // Supervisor Sw Int
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else if (ValidIntsM[5]) CauseM = 4'd5; // Supervisor Timer Int
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else if (BothInstrPageFaultM) CauseM = 4'd12;
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else if (BothInstrAccessFaultM) CauseM = 4'd1;
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else if (IllegalInstrFaultM) CauseM = 4'd2;
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// coverage off
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// Misaligned instructions cannot occur in rv64gc
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else if (InstrMisalignedFaultM) CauseM = 4'd0;
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// coverage on
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else if (BreakpointFaultM) CauseM = 4'd3;
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else if (EcallFaultM) CauseM = {2'b10, PrivilegeModeW};
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else if (StoreAmoMisalignedFaultM & ~P.ZICCLSM_SUPPORTED) CauseM = 4'd6; // misaligned faults are higher priority if they always are taken
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else if (LoadMisalignedFaultM & ~P.ZICCLSM_SUPPORTED) CauseM = 4'd4;
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else if (StoreAmoPageFaultM) CauseM = 4'd15;
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else if (LoadPageFaultM) CauseM = 4'd13;
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else if (StoreAmoAccessFaultM) CauseM = 4'd7;
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else if (LoadAccessFaultM) CauseM = 4'd5;
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else if (StoreAmoMisalignedFaultM & P.ZICCLSM_SUPPORTED) CauseM = 4'd6; // See priority in Privileged Spec 3.1.15
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else if (LoadMisalignedFaultM & P.ZICCLSM_SUPPORTED) CauseM = 4'd4;
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else CauseM = 4'd0;
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endmodule
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