mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-31 00:44:38 +00:00
84e4193db6
currently gets about 47k instrs correctly also fix gdb parsing to avoid accidently matching on function names
234 lines
7.0 KiB
Systemverilog
234 lines
7.0 KiB
Systemverilog
`include "wally-config.vh"
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module testbench_busybear();
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logic clk, reset;
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logic [`XLEN-1:0] WriteDataM, DataAdrM;
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logic [1:0] MemRWM;
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logic [31:0] GPIOPinsIn;
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logic [31:0] GPIOPinsOut, GPIOPinsEn;
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// instantiate device to be tested
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logic [`XLEN-1:0] PCF, ReadDataM;
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logic [31:0] InstrF;
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logic [7:0] ByteMaskM;
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logic InstrAccessFaultF, DataAccessFaultM;
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logic TimerIntM = 0, SwIntM = 0; // from CLINT
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logic ExtIntM = 0; // not yet connected
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// for now, seem to need these to be zero until we get a better idea
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assign InstrAccessFaultF = 0;
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assign DataAccessFaultM = 0;
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// instantiate processor and memories
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wallypipelinedhart dut(.*);
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// initialize test
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initial
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begin
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reset <= 1; # 22; reset <= 0;
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end
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// read pc trace file
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integer data_file_PC, scan_file_PC;
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initial begin
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data_file_PC = $fopen("../busybear-testgen/parsedPC.txt", "r");
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if (data_file_PC == 0) begin
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$display("file couldn't be opened");
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$stop;
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end
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end
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// read register trace file
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integer data_file_rf, scan_file_rf;
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initial begin
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data_file_rf = $fopen("../busybear-testgen/parsedRegs.txt", "r");
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if (data_file_rf == 0) begin
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$display("file couldn't be opened");
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$stop;
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end
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end
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// read memreads trace file
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integer data_file_memR, scan_file_memR;
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initial begin
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data_file_memR = $fopen("../busybear-testgen/parsedMemRead.txt", "r");
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if (data_file_memR == 0) begin
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$display("file couldn't be opened");
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$stop;
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end
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end
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// read memwrite trace file
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integer data_file_memW, scan_file_memW;
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initial begin
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data_file_memW = $fopen("../busybear-testgen/parsedMemWrite.txt", "r");
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if (data_file_memW == 0) begin
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$display("file couldn't be opened");
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$stop;
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end
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end
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logic [63:0] rfExpected[31:1];
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logic [63:0] pcExpected;
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// I apologize for this hack, I don't have a clue how to properly work with packed arrays
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logic [64*32:64] rf;
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genvar i;
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generate
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for(i=1; i<32; i++) begin
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assign rf[i*64+63:i*64] = dut.ieu.dp.regf.rf[i];
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end
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endgenerate
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always @(rf) begin
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for(int j=1; j<32; j++) begin
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if($feof(data_file_rf)) begin
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$display("no more rf data to read");
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$stop;
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end
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// read 31 integer registers
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scan_file_rf = $fscanf(data_file_rf, "%x\n", rfExpected[j]);
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// check things!
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if (rf[j*64+63 -: 64] != rfExpected[j]) begin
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$display("%t ps, instr %0d: rf[%0d] does not equal rf expected: %x, %x", $time, instrs, j, rf[j*64+63 -: 64], rfExpected[j]);
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// $stop;
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end
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end
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end
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logic [`XLEN-1:0] readAdrExpected;
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// this might need to change
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always @(MemRWM[1] or DataAdrM) begin
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if (MemRWM[1]) begin
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if($feof(data_file_memR)) begin
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$display("no more memR data to read");
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$stop;
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end
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scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
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scan_file_memR = $fscanf(data_file_memR, "%x\n", ReadDataM);
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if (DataAdrM != readAdrExpected) begin
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$display("%t ps, instr %0d: DataAdrM does not equal readAdrExpected: %x, %x", $time, instrs, DataAdrM, readAdrExpected);
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end
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end
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end
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logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;
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// this might need to change
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always @(WriteDataM or DataAdrM or ByteMaskM) begin
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#1;
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if (MemRWM[0]) begin
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if($feof(data_file_memW)) begin
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$display("no more memW data to read");
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$stop;
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end
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
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for(int i=0; i<8; i++) begin
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if (ByteMaskM[i]) begin
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if (writeDataExpected[i*8+7 -: 8] != WriteDataM[i*8+7 -: 8]) begin
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$display("%t ps, instr %0d: WriteDataM does not equal writeDataExpected: %x, %x", $time, instrs, WriteDataM, writeDataExpected);
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end
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end
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end
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if (writeAdrExpected != DataAdrM) begin
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$display("%t ps, instr %0d: DataAdrM does not equal writeAdrExpected: %x, %x", $time, instrs, DataAdrM, writeAdrExpected);
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end
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end
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end
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logic speculative;
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initial begin
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speculative = 0;
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speculative = 0;
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end
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logic [63:0] lastInstrF, lastPC, lastPC2;
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string PCtext, PCtext2;
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integer instrs;
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initial begin
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instrs = 0;
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end
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always @(PCF) begin
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lastInstrF = InstrF;
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lastPC <= PCF;
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lastPC2 <= lastPC;
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if (speculative && lastPC != pcExpected) begin
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speculative = (PCF != pcExpected);
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end
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else begin
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//if (~speculative) begin
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if($feof(data_file_PC)) begin
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$display("no more PC data to read");
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$stop;
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end
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// first read instruction
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext);
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if (PCtext != "ret") begin
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scan_file_PC = $fscanf(data_file_PC, "%s\n", PCtext2);
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PCtext = {PCtext, " ", PCtext2};
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end
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scan_file_PC = $fscanf(data_file_PC, "%x\n", InstrF);
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// then expected PC value
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scan_file_PC = $fscanf(data_file_PC, "%x\n", pcExpected);
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if (instrs <= 10 || (instrs <= 100 && instrs % 10 == 0) ||
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(instrs <= 1000 && instrs % 100 == 0) || (instrs <= 10000 && instrs % 1000 == 0) ||
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(instrs <= 100000 && instrs % 10000 == 0)) begin
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$display("loaded %0d instructions", instrs);
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end
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instrs += 1;
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// are we at a branch/jump?
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casex (lastInstrF[15:0])
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16'bXXXXXXXXX1101111, // JAL
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16'bXXXXXXXXX1100111, // JALR
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16'bXXXXXXXXX1100011, // B
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16'b110XXXXXXXXXXX01, // C.BEQZ
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16'b111XXXXXXXXXXX01, // C.BNEZ
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16'b101XXXXXXXXXXX01: // C.J
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speculative = 1;
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16'b1001000000000010: // C.EBREAK:
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speculative = 0; // tbh don't really know what should happen here
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16'b1000XXXXX0000010, // C.JR
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16'b1001XXXXX0000010: // C.JALR //this is RV64 only so no C.JAL
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speculative = 1;
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default:
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speculative = 0;
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endcase
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//check things!
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if ((~speculative) && (PCF !== pcExpected)) begin
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$display("%t ps, instr %0d: PC does not equal PC expected: %x, %x", $time, instrs, PCF, pcExpected);
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// $stop;
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end
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end
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end
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// Track names of instructions
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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instrNameDecTB dec(InstrF, InstrFName);
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instrTrackerTB it(clk, reset, dut.ieu.dp.FlushE,
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dut.ifu.InstrD, dut.ifu.InstrE,
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dut.ifu.InstrM, InstrW,
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InstrDName, InstrEName, InstrMName, InstrWName);
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// generate clock to sequence tests
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always
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begin
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clk <= 1; # 5; clk <= 0; # 5;
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end
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//// check results
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//always @(negedge clk)
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// begin
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// if(MemWrite) begin
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// if(DataAdr === 84 & WriteData === 71) begin
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// $display("Simulation succeeded");
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// $stop;
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// end else if (DataAdr !== 80) begin
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// $display("Simulation failed");
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// $stop;
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// end
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// end
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// end
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endmodule
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