David Harris 17cbdb53df Progress on Verilator simulation. Full adder compiles and runs. Wally builds.		2023-12-31 09:53:13 -08:00
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asm	Tested assembly language file for the pause example	2023-10-24 10:45:41 -07:00
C	Commented out unnecessary text segment in test.ld that causes RWX in LOAD segment warning	2023-05-14 03:58:08 -07:00
fp	Modify Makefile + software example for SP/DP/QP	2023-10-03 08:02:39 -05:00
link	Added badinstr test file	2023-03-21 06:57:03 -07:00
verilog	Progress on Verilator simulation. Full adder compiles and runs. Wally builds.	2023-12-31 09:53:13 -08:00