mirror of
https://github.com/openhwgroup/cvw
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38 lines
934 B
Plaintext
38 lines
934 B
Plaintext
# riscv-single.do
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#
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# Simulate with vsim -do riscvsingle.do
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# run with vsim -do "do wally-pipelined.do rv64ic riscvarchtest-64m"
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#onbreak {resume}
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# create library
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if [file exists work] {
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vdel -all
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}
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vlib work
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vlog -lint riscvsingle.sv
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vopt +acc work.testbench -o workopt
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vsim workopt
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view wave
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-- display input and output signals as hexadecimal values
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add wave -noupdate /testbench/clk
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add wave -noupdate /testbench/reset
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add wave -divider "Main Datapath"
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add wave -noupdate /testbench/dut/PC
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add wave -noupdate /testbench/dut/Instr
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add wave -noupdate /testbench/dut/rvsingle/dp/SrcA
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add wave -noupdate /testbench/dut/rvsingle/dp/SrcB
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add wave -noupdate /testbench/dut/rvsingle/dp/Result
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add wave -divider "Memory Bus"
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add wave -noupdate /testbench/MemWrite
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add wave -noupdate /testbench/DataAdr
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add wave -noupdate /testbench/WriteData
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add wave -noupdate /testbench/dut/ReadData
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-- Run the Simulation
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run -all
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view wave
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